| 3402aac7 |
1 | //------------------------------------------------------------------------------\r |
| 1e57a462 |
2 | //\r |
| 3 | // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r |
| 4 | //\r |
| 4059386c |
5 | // SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 1e57a462 |
6 | //\r |
| 7 | //------------------------------------------------------------------------------\r |
| 8 | \r |
| 9 | \r |
| 10 | \r |
| 11 | .text\r |
| 12 | .align 2\r |
| 13 | GCC_ASM_EXPORT(__aeabi_uldivmod)\r |
| 14 | \r |
| 3402aac7 |
15 | //\r |
| 1e57a462 |
16 | //UINT64\r |
| 17 | //EFIAPI\r |
| 18 | //__aeabi_uldivmod (\r |
| 3402aac7 |
19 | // IN UINT64 Dividend\r |
| 1e57a462 |
20 | // IN UINT64 Divisor\r |
| 21 | // )\r |
| 22 | //\r |
| 23 | ASM_PFX(__aeabi_uldivmod):\r |
| 24 | stmdb sp!, {r4, r5, r6, lr}\r |
| 25 | mov r4, r1\r |
| 26 | mov r5, r0\r |
| 27 | mov r6, #0 // 0x0\r |
| 28 | orrs ip, r3, r2, lsr #31\r |
| 29 | bne ASM_PFX(__aeabi_uldivmod_label1)\r |
| 30 | tst r2, r2\r |
| 31 | beq ASM_PFX(_ll_div0)\r |
| 32 | movs ip, r2, lsr #15\r |
| 33 | addeq r6, r6, #16 // 0x10\r |
| 34 | mov ip, r2, lsl r6\r |
| 35 | movs lr, ip, lsr #23\r |
| 36 | moveq ip, ip, lsl #8\r |
| 37 | addeq r6, r6, #8 // 0x8\r |
| 38 | movs lr, ip, lsr #27\r |
| 39 | moveq ip, ip, lsl #4\r |
| 40 | addeq r6, r6, #4 // 0x4\r |
| 41 | movs lr, ip, lsr #29\r |
| 42 | moveq ip, ip, lsl #2\r |
| 43 | addeq r6, r6, #2 // 0x2\r |
| 44 | movs lr, ip, lsr #30\r |
| 45 | moveq ip, ip, lsl #1\r |
| 46 | addeq r6, r6, #1 // 0x1\r |
| 47 | b ASM_PFX(_ll_udiv_small)\r |
| 48 | ASM_PFX(__aeabi_uldivmod_label1):\r |
| 49 | tst r3, #-2147483648 // 0x80000000\r |
| 50 | bne ASM_PFX(__aeabi_uldivmod_label2)\r |
| 51 | movs ip, r3, lsr #15\r |
| 52 | addeq r6, r6, #16 // 0x10\r |
| 53 | mov ip, r3, lsl r6\r |
| 54 | movs lr, ip, lsr #23\r |
| 55 | moveq ip, ip, lsl #8\r |
| 56 | addeq r6, r6, #8 // 0x8\r |
| 57 | movs lr, ip, lsr #27\r |
| 58 | moveq ip, ip, lsl #4\r |
| 59 | addeq r6, r6, #4 // 0x4\r |
| 60 | movs lr, ip, lsr #29\r |
| 61 | moveq ip, ip, lsl #2\r |
| 62 | addeq r6, r6, #2 // 0x2\r |
| 63 | movs lr, ip, lsr #30\r |
| 64 | addeq r6, r6, #1 // 0x1\r |
| 65 | rsb r3, r6, #32 // 0x20\r |
| 66 | moveq ip, ip, lsl #1\r |
| 67 | orr ip, ip, r2, lsr r3\r |
| 68 | mov lr, r2, lsl r6\r |
| 69 | b ASM_PFX(_ll_udiv_big)\r |
| 70 | ASM_PFX(__aeabi_uldivmod_label2):\r |
| 71 | mov ip, r3\r |
| 72 | mov lr, r2\r |
| 73 | b ASM_PFX(_ll_udiv_ginormous)\r |
| 3402aac7 |
74 | \r |
| 1e57a462 |
75 | ASM_PFX(_ll_udiv_small):\r |
| 76 | cmp r4, ip, lsl #1\r |
| 77 | mov r3, #0 // 0x0\r |
| 78 | subcs r4, r4, ip, lsl #1\r |
| 79 | addcs r3, r3, #2 // 0x2\r |
| 80 | cmp r4, ip\r |
| 81 | subcs r4, r4, ip\r |
| 82 | adcs r3, r3, #0 // 0x0\r |
| 83 | add r2, r6, #32 // 0x20\r |
| 84 | cmp r2, #32 // 0x20\r |
| 85 | rsb ip, ip, #0 // 0x0\r |
| 86 | bcc ASM_PFX(_ll_udiv_small_label1)\r |
| 87 | orrs r0, r4, r5, lsr #30\r |
| 88 | moveq r4, r5\r |
| 89 | moveq r5, #0 // 0x0\r |
| 90 | subeq r2, r2, #32 // 0x20\r |
| 91 | ASM_PFX(_ll_udiv_small_label1):\r |
| 92 | mov r1, #0 // 0x0\r |
| 93 | cmp r2, #16 // 0x10\r |
| 94 | bcc ASM_PFX(_ll_udiv_small_label2)\r |
| 95 | movs r0, r4, lsr #14\r |
| 96 | moveq r4, r4, lsl #16\r |
| 97 | addeq r1, r1, #16 // 0x10\r |
| 98 | ASM_PFX(_ll_udiv_small_label2):\r |
| 99 | sub lr, r2, r1\r |
| 100 | cmp lr, #8 // 0x8\r |
| 101 | bcc ASM_PFX(_ll_udiv_small_label3)\r |
| 102 | movs r0, r4, lsr #22\r |
| 103 | moveq r4, r4, lsl #8\r |
| 104 | addeq r1, r1, #8 // 0x8\r |
| 105 | ASM_PFX(_ll_udiv_small_label3):\r |
| 106 | rsb r0, r1, #32 // 0x20\r |
| 107 | sub r2, r2, r1\r |
| 108 | orr r4, r4, r5, lsr r0\r |
| 109 | mov r5, r5, lsl r1\r |
| 110 | cmp r2, #1 // 0x1\r |
| 111 | bcc ASM_PFX(_ll_udiv_small_label5)\r |
| 112 | sub r2, r2, #1 // 0x1\r |
| 113 | and r0, r2, #7 // 0x7\r |
| 114 | eor r0, r0, #7 // 0x7\r |
| 115 | adds r0, r0, r0, lsl #1\r |
| 116 | add pc, pc, r0, lsl #2\r |
| 117 | nop // (mov r0,r0)\r |
| 118 | ASM_PFX(_ll_udiv_small_label4):\r |
| 119 | adcs r5, r5, r5\r |
| 120 | adcs r4, ip, r4, lsl #1\r |
| 121 | rsbcc r4, ip, r4\r |
| 122 | adcs r5, r5, r5\r |
| 123 | adcs r4, ip, r4, lsl #1\r |
| 124 | rsbcc r4, ip, r4\r |
| 125 | adcs r5, r5, r5\r |
| 126 | adcs r4, ip, r4, lsl #1\r |
| 127 | rsbcc r4, ip, r4\r |
| 128 | adcs r5, r5, r5\r |
| 129 | adcs r4, ip, r4, lsl #1\r |
| 130 | rsbcc r4, ip, r4\r |
| 131 | adcs r5, r5, r5\r |
| 132 | adcs r4, ip, r4, lsl #1\r |
| 133 | rsbcc r4, ip, r4\r |
| 134 | adcs r5, r5, r5\r |
| 135 | adcs r4, ip, r4, lsl #1\r |
| 136 | rsbcc r4, ip, r4\r |
| 137 | adcs r5, r5, r5\r |
| 138 | adcs r4, ip, r4, lsl #1\r |
| 139 | rsbcc r4, ip, r4\r |
| 140 | adcs r5, r5, r5\r |
| 141 | adcs r4, ip, r4, lsl #1\r |
| 142 | sub r2, r2, #8 // 0x8\r |
| 143 | tst r2, r2\r |
| 144 | rsbcc r4, ip, r4\r |
| 145 | bpl ASM_PFX(_ll_udiv_small_label4)\r |
| 146 | ASM_PFX(_ll_udiv_small_label5):\r |
| 147 | mov r2, r4, lsr r6\r |
| 148 | bic r4, r4, r2, lsl r6\r |
| 149 | adcs r0, r5, r5\r |
| 150 | adc r1, r4, r4\r |
| 151 | add r1, r1, r3, lsl r6\r |
| 152 | mov r3, #0 // 0x0\r |
| 153 | ldmia sp!, {r4, r5, r6, pc}\r |
| 3402aac7 |
154 | \r |
| 1e57a462 |
155 | ASM_PFX(_ll_udiv_big):\r |
| 156 | subs r0, r5, lr\r |
| 157 | mov r3, #0 // 0x0\r |
| 158 | sbcs r1, r4, ip\r |
| 159 | movcs r5, r0\r |
| 160 | movcs r4, r1\r |
| 161 | adcs r3, r3, #0 // 0x0\r |
| 162 | subs r0, r5, lr\r |
| 163 | sbcs r1, r4, ip\r |
| 164 | movcs r5, r0\r |
| 165 | movcs r4, r1\r |
| 166 | adcs r3, r3, #0 // 0x0\r |
| 167 | subs r0, r5, lr\r |
| 168 | sbcs r1, r4, ip\r |
| 169 | movcs r5, r0\r |
| 170 | movcs r4, r1\r |
| 171 | adcs r3, r3, #0 // 0x0\r |
| 172 | mov r1, #0 // 0x0\r |
| 173 | rsbs lr, lr, #0 // 0x0\r |
| 174 | rsc ip, ip, #0 // 0x0\r |
| 175 | cmp r6, #16 // 0x10\r |
| 176 | bcc ASM_PFX(_ll_udiv_big_label1)\r |
| 177 | movs r0, r4, lsr #14\r |
| 178 | moveq r4, r4, lsl #16\r |
| 179 | addeq r1, r1, #16 // 0x10\r |
| 180 | ASM_PFX(_ll_udiv_big_label1):\r |
| 181 | sub r2, r6, r1\r |
| 182 | cmp r2, #8 // 0x8\r |
| 183 | bcc ASM_PFX(_ll_udiv_big_label2)\r |
| 184 | movs r0, r4, lsr #22\r |
| 185 | moveq r4, r4, lsl #8\r |
| 186 | addeq r1, r1, #8 // 0x8\r |
| 187 | ASM_PFX(_ll_udiv_big_label2):\r |
| 188 | rsb r0, r1, #32 // 0x20\r |
| 189 | sub r2, r6, r1\r |
| 190 | orr r4, r4, r5, lsr r0\r |
| 191 | mov r5, r5, lsl r1\r |
| 192 | cmp r2, #1 // 0x1\r |
| 193 | bcc ASM_PFX(_ll_udiv_big_label4)\r |
| 194 | sub r2, r2, #1 // 0x1\r |
| 195 | and r0, r2, #3 // 0x3\r |
| 196 | rsb r0, r0, #3 // 0x3\r |
| 197 | adds r0, r0, r0, lsl #1\r |
| 198 | add pc, pc, r0, lsl #3\r |
| 199 | nop // (mov r0,r0)\r |
| 200 | ASM_PFX(_ll_udiv_big_label3):\r |
| 201 | adcs r5, r5, r5\r |
| 202 | adcs r4, r4, r4\r |
| 203 | adcs r0, lr, r5\r |
| 204 | adcs r1, ip, r4\r |
| 205 | movcs r5, r0\r |
| 206 | movcs r4, r1\r |
| 207 | adcs r5, r5, r5\r |
| 208 | adcs r4, r4, r4\r |
| 209 | adcs r0, lr, r5\r |
| 210 | adcs r1, ip, r4\r |
| 211 | movcs r5, r0\r |
| 212 | movcs r4, r1\r |
| 213 | adcs r5, r5, r5\r |
| 214 | adcs r4, r4, r4\r |
| 215 | adcs r0, lr, r5\r |
| 216 | adcs r1, ip, r4\r |
| 217 | movcs r5, r0\r |
| 218 | movcs r4, r1\r |
| 219 | sub r2, r2, #4 // 0x4\r |
| 220 | adcs r5, r5, r5\r |
| 221 | adcs r4, r4, r4\r |
| 222 | adcs r0, lr, r5\r |
| 223 | adcs r1, ip, r4\r |
| 224 | tst r2, r2\r |
| 225 | movcs r5, r0\r |
| 226 | movcs r4, r1\r |
| 227 | bpl ASM_PFX(_ll_udiv_big_label3)\r |
| 228 | ASM_PFX(_ll_udiv_big_label4):\r |
| 229 | mov r1, #0 // 0x0\r |
| 230 | mov r2, r5, lsr r6\r |
| 231 | bic r5, r5, r2, lsl r6\r |
| 232 | adcs r0, r5, r5\r |
| 233 | adc r1, r1, #0 // 0x0\r |
| 234 | movs lr, r3, lsl r6\r |
| 235 | mov r3, r4, lsr r6\r |
| 236 | bic r4, r4, r3, lsl r6\r |
| 237 | adc r1, r1, #0 // 0x0\r |
| 238 | adds r0, r0, lr\r |
| 239 | orr r2, r2, r4, ror r6\r |
| 240 | adc r1, r1, #0 // 0x0\r |
| 241 | ldmia sp!, {r4, r5, r6, pc}\r |
| 3402aac7 |
242 | \r |
| 1e57a462 |
243 | ASM_PFX(_ll_udiv_ginormous):\r |
| 244 | subs r2, r5, lr\r |
| 245 | mov r1, #0 // 0x0\r |
| 246 | sbcs r3, r4, ip\r |
| 247 | adc r0, r1, r1\r |
| 248 | movcc r2, r5\r |
| 249 | movcc r3, r4\r |
| 250 | ldmia sp!, {r4, r5, r6, pc}\r |
| 3402aac7 |
251 | \r |
| 1e57a462 |
252 | ASM_PFX(_ll_div0):\r |
| 253 | ldmia sp!, {r4, r5, r6, lr}\r |
| 254 | mov r0, #0 // 0x0\r |
| 255 | mov r1, #0 // 0x0\r |
| 256 | b ASM_PFX(__aeabi_ldiv0)\r |
| 3402aac7 |
257 | \r |
| 1e57a462 |
258 | ASM_PFX(__aeabi_ldiv0):\r |
| 259 | bx r14\r |
| 260 | \r |
| 261 | \r |
projects / mirror_edk2.git / blame