projects / mirror_edk2.git / blame
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| ae52e921 LL |
1 | /** @file\r |
| 2 | Differentiated System Description Table Fields (SSDT)\r | |
| 3 | \r | |
| 4 | Copyright (c) 2014-2015, ARM Ltd. All rights reserved.<BR>\r | |
| 5 | This program and the accompanying materials\r | |
| 6 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 7 | which accompanies this distribution. The full text of the license may be found at\r | |
| 8 | http://opensource.org/licenses/bsd-license.php\r | |
| 9 | \r | |
| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 12 | \r | |
| 13 | **/\r | |
| 14 | \r | |
| 15 | #include "ArmPlatform.h"\r | |
| 16 | \r | |
| 17 | /*\r | |
| 18 | See Reference [1] 6.2.12\r | |
| 19 | "There are two ways that _PRT can be used. ...\r | |
| 20 | In the second model, the PCI interrupts are hardwired to specific interrupt\r | |
| 21 | inputs on the interrupt controller and are not configurable. In this case,\r | |
| 22 | the Source field in _PRT does not reference a device, but instead contains\r | |
| 23 | the value zero, and the Source Index field contains the global system\r | |
| 24 | interrupt to which the PCI interrupt is hardwired."\r | |
| 25 | */\r | |
| 26 | #define PRT_ENTRY(Address, Pin, Interrupt) \\r | |
| 27 | Package (4) { \\r | |
| 28 | Address, /* uses the same format as _ADR */ \\r | |
| 29 | Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD). */ \\r | |
| 30 | Zero, /* allocated from the global interrupt pool. */ \\r | |
| 31 | Interrupt /* global system interrupt number */ \\r | |
| 32 | }\r | |
| 33 | \r | |
| 34 | /*\r | |
| 35 | See Reference [1] 6.1.1\r | |
| 36 | "High word–Device #, Low word–Function #. (for example, device 3, function 2 is\r | |
| 37 | 0x00030002). To refer to all the functions on a device #, use a function number of FFFF)."\r | |
| 38 | */\r | |
| 39 | #define ROOT_PRT_ENTRY(Pin, Interrupt) PRT_ENTRY(0x0000FFFF, Pin, Interrupt)\r | |
| 40 | // Device 0 for Bridge.\r | |
| 41 | \r | |
| 42 | \r | |
| 43 | DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM_REVISION) {\r | |
| 44 | Scope(_SB) {\r | |
| 45 | //\r | |
| 46 | // PCI Root Complex\r | |
| 47 | //\r | |
| 48 | Device(PCI0)\r | |
| 49 | {\r | |
| 50 | Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge\r | |
| 51 | Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge\r | |
| 52 | Name(_SEG, Zero) // PCI Segment Group number\r | |
| 53 | Name(_BBN, Zero) // PCI Base Bus Number\r | |
| 54 | \r | |
| 55 | // Root Complex 0\r | |
| 56 | Device (RP0) {\r | |
| 57 | Name(_ADR, 0xF0000000) // Dev 0, Func 0\r | |
| 58 | }\r | |
| 59 | \r | |
| 60 | // PCI Routing Table\r | |
| 61 | Name(_PRT, Package() {\r | |
| 62 | ROOT_PRT_ENTRY(0, 168), // INTA\r | |
| 63 | ROOT_PRT_ENTRY(1, 169), // INTB\r | |
| 64 | ROOT_PRT_ENTRY(2, 170), // INTC\r | |
| 65 | ROOT_PRT_ENTRY(3, 171), // INTD\r | |
| 66 | })\r | |
| 67 | // Root complex resources\r | |
| 68 | Method (_CRS, 0, Serialized) {\r | |
| 69 | Name (RBUF, ResourceTemplate () {\r | |
| 70 | WordBusNumber ( // Bus numbers assigned to this root\r | |
| 71 | ResourceProducer,\r | |
| 72 | MinFixed, MaxFixed, PosDecode,\r | |
| 73 | 0, // AddressGranularity\r | |
| 74 | 0, // AddressMinimum - Minimum Bus Number\r | |
| 75 | 255, // AddressMaximum - Maximum Bus Number\r | |
| 76 | 0, // AddressTranslation - Set to 0\r | |
| 77 | 256 // RangeLength - Number of Busses\r | |
| 78 | )\r | |
| 79 | \r | |
| 80 | DWordMemory ( // 32-bit BAR Windows\r | |
| 81 | ResourceProducer, PosDecode,\r | |
| 82 | MinFixed, MaxFixed,\r | |
| 83 | Cacheable, ReadWrite,\r | |
| 84 | 0x00000000, // Granularity\r | |
| 85 | 0x50000000, // Min Base Address\r | |
| 86 | 0x57FFFFFF, // Max Base Address\r | |
| 87 | 0x00000000, // Translate\r | |
| 88 | 0x08000000 // Length\r | |
| 89 | )\r | |
| 90 | \r | |
| 91 | QWordMemory ( // 64-bit BAR Windows\r | |
| 92 | ResourceProducer, PosDecode,\r | |
| 93 | MinFixed, MaxFixed,\r | |
| 94 | Cacheable, ReadWrite,\r | |
| 95 | 0x00000000, // Granularity\r | |
| 96 | 0x4000000000, // Min Base Address\r | |
| 97 | 0x40FFFFFFFF, // Max Base Address\r | |
| 98 | 0x00000000, // Translate\r | |
| 99 | 0x100000000 // Length\r | |
| 100 | )\r | |
| 101 | \r | |
| 102 | DWordIo ( // IO window\r | |
| 103 | ResourceProducer,\r | |
| 104 | MinFixed,\r | |
| 105 | MaxFixed,\r | |
| 106 | PosDecode,\r | |
| 107 | EntireRange,\r | |
| 108 | 0x00000000, // Granularity\r | |
| 109 | 0x5f800000, // Min Base Address\r | |
| 110 | 0x5fffffff, // Max Base Address\r | |
| 111 | 0x5f800000, // Translate\r | |
| 112 | 0x00800000 // Length\r | |
| 113 | )\r | |
| 114 | }) // Name(RBUF)\r | |
| 115 | \r | |
| 116 | Return (RBUF)\r | |
| 117 | } // Method(_CRS)\r | |
| 118 | \r | |
| 119 | //\r | |
| 120 | // OS Control Handoff\r | |
| 121 | //\r | |
| 122 | Name(SUPP, Zero) // PCI _OSC Support Field value\r | |
| 123 | Name(CTRL, Zero) // PCI _OSC Control Field value\r | |
| 124 | \r | |
| 125 | /*\r | |
| 126 | See [1] 6.2.10, [2] 4.5\r | |
| 127 | */\r | |
| 128 | Method(_OSC,4) {\r | |
| 129 | // Check for proper UUID\r | |
| 130 | If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {\r | |
| 131 | // Create DWord-adressable fields from the Capabilities Buffer\r | |
| 132 | CreateDWordField(Arg3,0,CDW1)\r | |
| 133 | CreateDWordField(Arg3,4,CDW2)\r | |
| 134 | CreateDWordField(Arg3,8,CDW3)\r | |
| 135 | \r | |
| 136 | // Save Capabilities DWord2 & 3\r | |
| 137 | Store(CDW2,SUPP)\r | |
| 138 | Store(CDW3,CTRL)\r | |
| 139 | \r | |
| 140 | // Only allow native hot plug control if OS supports:\r | |
| 141 | // * ASPM\r | |
| 142 | // * Clock PM\r | |
| 143 | // * MSI/MSI-X\r | |
| 144 | If(LNotEqual(And(SUPP, 0x16), 0x16)) {\r | |
| 145 | And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)\r | |
| 146 | }\r | |
| 147 | \r | |
| 148 | // Always allow native PME, AER (no dependencies)\r | |
| 149 | \r | |
| 150 | // Never allow SHPC (no SHPC controller in this system)\r | |
| 151 | And(CTRL,0x1D,CTRL)\r | |
| 152 | \r | |
| 153 | #if 0\r | |
| 154 | If(LNot(And(CDW1,1))) { // Query flag clear?\r | |
| 155 | // Disable GPEs for features granted native control.\r | |
| 156 | If(And(CTRL,0x01)) { // Hot plug control granted?\r | |
| 157 | Store(0,HPCE) // clear the hot plug SCI enable bit\r | |
| 158 | Store(1,HPCS) // clear the hot plug SCI status bit\r | |
| 159 | }\r | |
| 160 | If(And(CTRL,0x04)) { // PME control granted?\r | |
| 161 | Store(0,PMCE) // clear the PME SCI enable bit\r | |
| 162 | Store(1,PMCS) // clear the PME SCI status bit\r | |
| 163 | }\r | |
| 164 | If(And(CTRL,0x10)) { // OS restoring PCIe cap structure?\r | |
| 165 | // Set status to not restore PCIe cap structure\r | |
| 166 | // upon resume from S3\r | |
| 167 | Store(1,S3CR)\r | |
| 168 | }\r | |
| 169 | }\r | |
| 170 | #endif\r | |
| 171 | \r | |
| 172 | If(LNotEqual(Arg1,One)) { // Unknown revision\r | |
| 173 | Or(CDW1,0x08,CDW1)\r | |
| 174 | }\r | |
| 175 | \r | |
| 176 | If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked\r | |
| 177 | Or(CDW1,0x10,CDW1)\r | |
| 178 | }\r | |
| 179 | // Update DWORD3 in the buffer\r | |
| 180 | Store(CTRL,CDW3)\r | |
| 181 | Return(Arg3)\r | |
| 182 | } Else {\r | |
| 183 | Or(CDW1,4,CDW1) // Unrecognized UUID\r | |
| 184 | Return(Arg3)\r | |
| 185 | }\r | |
| 186 | } // End _OSC\r | |
| 187 | } // PCI0\r | |
| 188 | }\r | |
| 189 | }\r |