[mirror_edk2.git] / ArmPlatformPkg / ArmJunoPkg / AcpiTables / Madt.aslc

/** @file\r
*  Multiple APIC Description Table (MADT)\r
*\r
*  Copyright (c) 2012 - 2015, ARM Limited. All rights reserved.\r
*\r
*  This program and the accompanying materials\r
*  are licensed and made available under the terms and conditions of the BSD License\r
*  which accompanies this distribution.  The full text of the license may be found at\r
*  http://opensource.org/licenses/bsd-license.php\r
*\r
*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
*\r
**/\r
\r
#include "ArmPlatform.h"\r
#include <Library/AcpiLib.h>\r
#include <Library/ArmLib.h>\r
#include <Library/PcdLib.h>\r
#include <IndustryStandard/Acpi.h>\r
\r
//\r
// Multiple APIC Description Table\r
//\r
#ifdef ARM_JUNO_ACPI_5_0\r
  #pragma pack (1)\r
\r
  typedef struct {\r
    EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER   Header;\r
    EFI_ACPI_5_0_GIC_STRUCTURE                            GicInterfaces[FixedPcdGet32 (PcdCoreCount)];\r
    EFI_ACPI_5_0_GIC_DISTRIBUTOR_STRUCTURE                GicDistributor;\r
  } EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE;\r
\r
  #pragma pack ()\r
\r
  EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {\r
    {\r
      ARM_ACPI_HEADER (\r
        EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,\r
        EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE,\r
        EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION\r
      ),\r
      //\r
      // MADT specific fields\r
      //\r
      0, // LocalApicAddress\r
      0, // Flags\r
    },\r
    {\r
      // Format: EFI_ACPI_5_0_GIC_STRUCTURE_INIT(GicId, AcpiCpuId, Flags, PmuIrq, GicBase)\r
      // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GIC Structure of\r
      //       ACPI v5.0).\r
      //       On Juno we can change the primary CPU changing the SCC register. It is not currently supported in the\r
      //       Trusted Firmware. When supported, we will need to code to dynamically change the ordering.\r
      //       For now we leave CPU2 (A53-0) at the first position.\r
      //       The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses\r
      //       the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.\r
      EFI_ACPI_5_0_GIC_STRUCTURE_INIT(2, 0, EFI_ACPI_5_0_GIC_ENABLED, 50, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-0\r
      EFI_ACPI_5_0_GIC_STRUCTURE_INIT(3, 1, EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-1\r
      EFI_ACPI_5_0_GIC_STRUCTURE_INIT(4, 2, EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-2\r
      EFI_ACPI_5_0_GIC_STRUCTURE_INIT(5, 3, EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-3\r
      EFI_ACPI_5_0_GIC_STRUCTURE_INIT(0, 4, EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A57-0\r
      EFI_ACPI_5_0_GIC_STRUCTURE_INIT(1, 5, EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet32 (PcdGicInterruptInterfaceBase))  // A57-1\r
    },\r
    EFI_ACPI_5_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0)\r
  };\r
#else\r
  #pragma pack (1)\r
\r
  typedef struct {\r
    EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER   Header;\r
    EFI_ACPI_5_1_GIC_STRUCTURE                            GicInterfaces[FixedPcdGet32 (PcdCoreCount)];\r
    EFI_ACPI_5_0_GIC_DISTRIBUTOR_STRUCTURE                GicDistributor;\r
    EFI_ACPI_6_0_GIC_MSI_FRAME_STRUCTURE                  MsiFrame;\r
  } EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE;\r
\r
  #pragma pack ()\r
\r
  EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {\r
    {\r
      ARM_ACPI_HEADER (\r
        EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,\r
        EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE,\r
        EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION\r
      ),\r
      //\r
      // MADT specific fields\r
      //\r
      0, // LocalApicAddress\r
      0, // Flags\r
    },\r
    {\r
      // Format: EFI_ACPI_5_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase,\r
      //                                          GsivId, GicRBase, Mpidr)\r
      // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of\r
      //       ACPI v5.1).\r
      //       On Juno we can change the primary CPU changing the SCC register. It is not currently supported in the\r
      //       Trusted Firmware. When supported, we will need to code to dynamically change the ordering.\r
      //       For now we leave CPU2 (A53-0) at the first position.\r
      //       The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses\r
      //       the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.\r
      EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-0\r
          2, 0, GET_MPID(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 50, FixedPcdGet32 (PcdGicInterruptInterfaceBase),\r
          0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),\r
      EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-1\r
          3, 1, GET_MPID(1, 1),  EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet32 (PcdGicInterruptInterfaceBase),\r
          0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),\r
      EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-2\r
          4, 2, GET_MPID(1, 2),  EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet32 (PcdGicInterruptInterfaceBase),\r
          0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),\r
      EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-3\r
          5, 3, GET_MPID(1, 3),  EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet32 (PcdGicInterruptInterfaceBase),\r
          0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),\r
      EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A57-0\r
          0, 4, GET_MPID(0, 0),  EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet32 (PcdGicInterruptInterfaceBase),\r
          0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),\r
      EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A57-1\r
          1, 5, GET_MPID(0, 1),  EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet32 (PcdGicInterruptInterfaceBase),\r
          0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),\r
    },\r
    EFI_ACPI_5_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0),\r
    // Format: EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(GicMsiFrameId, PhysicalBaseAddress, Flags, SPICount, SPIBase)\r
    EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0, ARM_JUNO_GIV2M_MSI_BASE, 0, ARM_JUNO_GIV2M_MSI_SPI_COUNT, ARM_JUNO_GIV2M_MSI_SPI_BASE)\r
  };\r
#endif\r
\r
//\r
// Reference the table being generated to prevent the optimizer from removing the\r
// data structure from the executable\r
//\r
VOID* CONST ReferenceAcpiTable = &Madt;\r
Commit	Line	Data
3399d5be OM	1	/** @file\r
	2	* Multiple APIC Description Table (MADT)\r
	3	*\r
2596e61a	4	* Copyright (c) 2012 - 2015, ARM Limited. All rights reserved.\r
3399d5be OM	5	*\r
	6	* This program and the accompanying materials\r
	7	* are licensed and made available under the terms and conditions of the BSD License\r
	8	* which accompanies this distribution. The full text of the license may be found at\r
	9	* http://opensource.org/licenses/bsd-license.php\r
	10	*\r
	11	* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	*\r
	14	**/\r
	15	\r
	16	#include "ArmPlatform.h"\r
	17	#include <Library/AcpiLib.h>\r
2596e61a	18	#include <Library/ArmLib.h>\r
3399d5be OM	19	#include <Library/PcdLib.h>\r
	20	#include <IndustryStandard/Acpi.h>\r
	21	\r
3399d5be OM	22	//\r
	23	// Multiple APIC Description Table\r
	24	//\r
2596e61a OM	25	#ifdef ARM_JUNO_ACPI_5_0\r
	26	#pragma pack (1)\r
	27	\r
	28	typedef struct {\r
58a1e940	29	EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;\r
2596e61a OM	30	EFI_ACPI_5_0_GIC_STRUCTURE GicInterfaces[FixedPcdGet32 (PcdCoreCount)];\r
2596e61a OM	31	EFI_ACPI_5_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;\r
58a1e940	32	} EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE;\r
2596e61a OM	33	\r
	34	#pragma pack ()\r
	35	\r
58a1e940	36	EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {\r
2596e61a OM	37	{\r
2596e61a OM	38	ARM_ACPI_HEADER (\r
58a1e940 SH	39	EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,\r
	40	EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE,\r
	41	EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION\r
2596e61a OM	42	),\r
	43	//\r
	44	// MADT specific fields\r
	45	//\r
	46	0, // LocalApicAddress\r
	47	0, // Flags\r
	48	},\r
	49	{\r
	50	// Format: EFI_ACPI_5_0_GIC_STRUCTURE_INIT(GicId, AcpiCpuId, Flags, PmuIrq, GicBase)\r
	51	// Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GIC Structure of\r
	52	// ACPI v5.0).\r
	53	// On Juno we can change the primary CPU changing the SCC register. It is not currently supported in the\r
	54	// Trusted Firmware. When supported, we will need to code to dynamically change the ordering.\r
	55	// For now we leave CPU2 (A53-0) at the first position.\r
	56	// The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses\r
	57	// the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.\r
	58	EFI_ACPI_5_0_GIC_STRUCTURE_INIT(2, 0, EFI_ACPI_5_0_GIC_ENABLED, 50, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-0\r
	59	EFI_ACPI_5_0_GIC_STRUCTURE_INIT(3, 1, EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-1\r
	60	EFI_ACPI_5_0_GIC_STRUCTURE_INIT(4, 2, EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-2\r
	61	EFI_ACPI_5_0_GIC_STRUCTURE_INIT(5, 3, EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A53-3\r
	62	EFI_ACPI_5_0_GIC_STRUCTURE_INIT(0, 4, EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet32 (PcdGicInterruptInterfaceBase)), // A57-0\r
	63	EFI_ACPI_5_0_GIC_STRUCTURE_INIT(1, 5, EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet32 (PcdGicInterruptInterfaceBase)) // A57-1\r
	64	},\r
	65	EFI_ACPI_5_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0)\r
	66	};\r
	67	#else\r
	68	#pragma pack (1)\r
	69	\r
	70	typedef struct {\r
58a1e940	71	EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;\r
2596e61a OM	72	EFI_ACPI_5_1_GIC_STRUCTURE GicInterfaces[FixedPcdGet32 (PcdCoreCount)];\r
2596e61a OM	73	EFI_ACPI_5_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;\r
44a35695	74	EFI_ACPI_6_0_GIC_MSI_FRAME_STRUCTURE MsiFrame;\r
58a1e940	75	} EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE;\r
2596e61a OM	76	\r
	77	#pragma pack ()\r
	78	\r
58a1e940	79	EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {\r
2596e61a OM	80	{\r
2596e61a OM	81	ARM_ACPI_HEADER (\r
58a1e940 SH	82	EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,\r
	83	EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE,\r
	84	EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION\r
2596e61a OM	85	),\r
	86	//\r
	87	// MADT specific fields\r
	88	//\r
	89	0, // LocalApicAddress\r
	90	0, // Flags\r
	91	},\r
	92	{\r
	93	// Format: EFI_ACPI_5_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase,\r
	94	// GsivId, GicRBase, Mpidr)\r
	95	// Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of\r
	96	// ACPI v5.1).\r
	97	// On Juno we can change the primary CPU changing the SCC register. It is not currently supported in the\r
	98	// Trusted Firmware. When supported, we will need to code to dynamically change the ordering.\r
	99	// For now we leave CPU2 (A53-0) at the first position.\r
	100	// The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses\r
	101	// the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.\r
	102	EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-0\r
	103	2, 0, GET_MPID(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 50, FixedPcdGet32 (PcdGicInterruptInterfaceBase),\r
	104	0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),\r
	105	EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-1\r
	106	3, 1, GET_MPID(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet32 (PcdGicInterruptInterfaceBase),\r
	107	0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),\r
	108	EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-2\r
	109	4, 2, GET_MPID(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet32 (PcdGicInterruptInterfaceBase),\r
	110	0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),\r
	111	EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-3\r
	112	5, 3, GET_MPID(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet32 (PcdGicInterruptInterfaceBase),\r
	113	0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),\r
	114	EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A57-0\r
	115	0, 4, GET_MPID(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet32 (PcdGicInterruptInterfaceBase),\r
	116	0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),\r
	117	EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A57-1\r
	118	1, 5, GET_MPID(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet32 (PcdGicInterruptInterfaceBase),\r
	119	0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),\r
	120	},\r
44a35695	121	EFI_ACPI_5_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0),\r
efcc052b JL	122	// Format: EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(GicMsiFrameId, PhysicalBaseAddress, Flags, SPICount, SPIBase)\r
efcc052b JL	123	EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0, ARM_JUNO_GIV2M_MSI_BASE, 0, ARM_JUNO_GIV2M_MSI_SPI_COUNT, ARM_JUNO_GIV2M_MSI_SPI_BASE)\r
2596e61a OM	124	};\r
2596e61a OM	125	#endif\r
3399d5be	126	\r
9bdf791f AB	127	//\r
	128	// Reference the table being generated to prevent the optimizer from removing the\r
	129	// data structure from the executable\r
	130	//\r
	131	VOID* CONST ReferenceAcpiTable = &Madt;\r