[mirror_edk2.git] / ArmPlatformPkg / ArmPlatformPkg.dec

#/** @file\r
#\r
#  Copyright (c) 2011, ARM Limited. All rights reserved.\r
#  \r
#  This program and the accompanying materials                          \r
#  are licensed and made available under the terms and conditions of the BSD License         \r
#  which accompanies this distribution.  The full text of the license may be found at        \r
#  http://opensource.org/licenses/bsd-license.php                                            \r
#\r
#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
#\r
#**/\r
\r
[Defines]\r
  DEC_SPECIFICATION              = 0x00010005\r
  PACKAGE_NAME                   = ArmPlatformPkg\r
  PACKAGE_GUID                   = 3308e0a0-1d94-11e0-915c-0002a5d5c51b \r
  PACKAGE_VERSION                = 0.1\r
\r
################################################################################\r
#\r
# Include Section - list of Include Paths that are provided by this package.\r
#                   Comments are used for Keywords and Module Types.\r
#\r
# Supported Module Types:\r
#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
#\r
################################################################################\r
[Includes.common]\r
  Include                        # Root include for the package\r
\r
[Guids.common]\r
  gArmPlatformTokenSpaceGuid   = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }\r
  #\r
  # Following Guid must match FILE_GUID in MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf\r
  #\r
  gVariableRuntimeDxeFileGuid = { 0xcbd2e4d5, 0x7068, 0x4ff5, { 0xb4, 0x62, 0x98, 0x22, 0xb4, 0xad, 0x8d, 0x60 } }\r
\r
[PcdsFeatureFlag.common]\r
  # Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0.\r
  gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping|FALSE|BOOLEAN|0x00000012\r
  \r
  gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE|BOOLEAN|0x00000001\r
  gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|FALSE|BOOLEAN|0x00000002\r
  gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004\r
\r
[PcdsFixedAtBuild.common]\r
  # These PCDs should be FeaturePcds. But we used these PCDs as an '#if' in an ASM file.\r
  # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.\r
  gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|0|UINT32|0x00000003\r
  gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038\r
    \r
  # Stack for CPU Cores in Secure Mode\r
  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT32|0x00000005\r
  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000|UINT32|0x00000036\r
  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000|UINT32|0x00000006\r
\r
  # Stack for CPU Cores in Secure Monitor Mode\r
  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007\r
  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000|UINT32|0x00000008\r
\r
  # Stack for CPU Cores in Non Secure Mode\r
  gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT32|0x00000009\r
  gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037\r
  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000|UINT32|0x0000000A\r
    \r
  # Size of the region used by UEFI in permanent memory (Reserved 128MB by default)\r
  gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015\r
\r
  # Size to reserve in the primary core stack for PEI Global Variables\r
  #  = sizeof(UINTN) /* PcdPeiServicePtr or HobListPtr */\r
  gArmPlatformTokenSpaceGuid.PcdPeiGlobalVariableSize|0x4|UINT32|0x00000016\r
  # PeiServicePtr and HobListPtr shares the same location in the PEI Global Variable list\r
  # PeiServicePtr is only valid with PEI Core and HobListPtr only when the PEI Core is skipped. \r
  gArmPlatformTokenSpaceGuid.PcdPeiServicePtrGlobalOffset|0x0|UINT32|0x00000017\r
  gArmPlatformTokenSpaceGuid.PcdHobListPtrGlobalOffset|0x0|UINT32|0x00000018\r
\r
  #\r
  # ARM Primecells\r
  #\r
\r
  ## SP804 DualTimer\r
  gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz|1|UINT32|0x0000001D\r
  gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|0|UINT32|0x0000001E\r
  gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0|UINT32|0x0000002A\r
  gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0|UINT32|0x0000002B\r
  gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0|UINT32|0x0000002C\r
\r
  ## SP805 Watchdog\r
  gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0|UINT32|0x00000023\r
  gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|32000|UINT32|0x00000021\r
\r
  ## PL011 UART\r
  gArmPlatformTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0x00000000|UINT32|0x0000001F\r
  gArmPlatformTokenSpaceGuid.PcdUartDefaultTimeout|0x00000000|UINT32|0x00000020\r
\r
  ## PL031 RealTimeClock\r
  gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024\r
  gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022\r
\r
  ## PL061 GPIO\r
  gArmPlatformTokenSpaceGuid.PcdPL061GpioBase|0x0|UINT32|0x00000025\r
  \r
  ## PL111 Lcd\r
  gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026\r
  gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027\r
  \r
  ## PL180 MCI\r
  gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x00000028\r
  gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00000029\r
\r
  #\r
  # BDS - Boot Manager\r
  #\r
  gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Platform"|VOID*|0x00000019\r
  gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Default Boot Device"|VOID*|0x0000000C\r
  gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L""|VOID*|0x0000000D\r
  gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L""|VOID*|0x0000000E\r
  gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|""|VOID*|0x000000F\r
  # PcdDefaultBootType define the type of the binary pointed by PcdDefaultBootDevicePath: \r
  #  - 0 = an EFI application\r
  #  - 1 = a Linux kernel with ATAG support\r
  #  - 2 = a Linux kernel with FDT support\r
  gArmPlatformTokenSpaceGuid.PcdDefaultBootType|0|UINT32|0x00000010\r
  gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L""|VOID*|0x00000011\r
  \r
  ## Timeout value for displaying progressing bar in before boot OS.\r
  #  According to UEFI 2.0 spec, the default TimeOut should be 0xffff.\r
  gArmPlatformTokenSpaceGuid.PcdPlatformBootTimeOut|0xffff|UINT16|0x0000001A\r
  \r
  gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L""|VOID*|0x0000001B\r
  gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L""|VOID*|0x0000001C\r
  \r
Commit	Line	Data
11c20f4e	1	#/** @file\r
	2	#\r
	3	# Copyright (c) 2011, ARM Limited. All rights reserved.\r
	4	# \r
	5	# This program and the accompanying materials \r
	6	# are licensed and made available under the terms and conditions of the BSD License \r
	7	# which accompanies this distribution. The full text of the license may be found at \r
	8	# http://opensource.org/licenses/bsd-license.php \r
	9	#\r
	10	# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	11	# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
	12	#\r
	13	#**/\r
	14	\r
	15	[Defines]\r
	16	DEC_SPECIFICATION = 0x00010005\r
	17	PACKAGE_NAME = ArmPlatformPkg\r
	18	PACKAGE_GUID = 3308e0a0-1d94-11e0-915c-0002a5d5c51b \r
	19	PACKAGE_VERSION = 0.1\r
	20	\r
	21	################################################################################\r
	22	#\r
	23	# Include Section - list of Include Paths that are provided by this package.\r
	24	# Comments are used for Keywords and Module Types.\r
	25	#\r
	26	# Supported Module Types:\r
	27	# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
	28	#\r
	29	################################################################################\r
	30	[Includes.common]\r
	31	Include # Root include for the package\r
	32	\r
	33	[Guids.common]\r
	34	gArmPlatformTokenSpaceGuid = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }\r
	35	#\r
	36	# Following Guid must match FILE_GUID in MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf\r
	37	#\r
	38	gVariableRuntimeDxeFileGuid = { 0xcbd2e4d5, 0x7068, 0x4ff5, { 0xb4, 0x62, 0x98, 0x22, 0xb4, 0xad, 0x8d, 0x60 } }\r
	39	\r
	40	[PcdsFeatureFlag.common]\r
	41	# Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0.\r
	42	gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping\|FALSE\|BOOLEAN\|0x00000012\r
	43	\r
	44	gArmPlatformTokenSpaceGuid.PcdStandalone\|TRUE\|BOOLEAN\|0x00000001\r
	45	gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec\|FALSE\|BOOLEAN\|0x00000002\r
	46	gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores\|FALSE\|BOOLEAN\|0x00000004\r
	47	\r
	48	[PcdsFixedAtBuild.common]\r
	49	# These PCDs should be FeaturePcds. But we used these PCDs as an '#if' in an ASM file.\r
	50	# Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.\r
	51	gArmPlatformTokenSpaceGuid.PcdMPCoreSupport\|0\|UINT32\|0x00000003\r
2dbcb8f0	52	gArmPlatformTokenSpaceGuid.PcdClusterCount\|1\|UINT32\|0x00000038\r
2dbcb8f0	53	\r
11c20f4e	54	# Stack for CPU Cores in Secure Mode\r
11c20f4e	55	gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase\|0\|UINT32\|0x00000005\r
2dbcb8f0	56	gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize\|0x10000\|UINT32\|0x00000036\r
2dbcb8f0	57	gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize\|0x1000\|UINT32\|0x00000006\r
11c20f4e	58	\r
	59	# Stack for CPU Cores in Secure Monitor Mode\r
	60	gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase\|0\|UINT32\|0x00000007\r
2dbcb8f0	61	gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize\|0x1000\|UINT32\|0x00000008\r
11c20f4e	62	\r
11c20f4e	63	# Stack for CPU Cores in Non Secure Mode\r
2dbcb8f0	64	gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase\|0\|UINT32\|0x00000009\r
	65	gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize\|0x10000\|UINT32\|0x00000037\r
	66	gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize\|0x1000\|UINT32\|0x0000000A\r
11c20f4e	67	\r
	68	# Size of the region used by UEFI in permanent memory (Reserved 128MB by default)\r
	69	gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize\|0x08000000\|UINT32\|0x00000015\r
	70	\r
	71	# Size to reserve in the primary core stack for PEI Global Variables\r
	72	# = sizeof(UINTN) /* PcdPeiServicePtr or HobListPtr */\r
	73	gArmPlatformTokenSpaceGuid.PcdPeiGlobalVariableSize\|0x4\|UINT32\|0x00000016\r
	74	# PeiServicePtr and HobListPtr shares the same location in the PEI Global Variable list\r
	75	# PeiServicePtr is only valid with PEI Core and HobListPtr only when the PEI Core is skipped. \r
	76	gArmPlatformTokenSpaceGuid.PcdPeiServicePtrGlobalOffset\|0x0\|UINT32\|0x00000017\r
	77	gArmPlatformTokenSpaceGuid.PcdHobListPtrGlobalOffset\|0x0\|UINT32\|0x00000018\r
	78	\r
	79	#\r
	80	# ARM Primecells\r
	81	#\r
	82	\r
	83	## SP804 DualTimer\r
	84	gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz\|1\|UINT32\|0x0000001D\r
	85	gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum\|0\|UINT32\|0x0000001E\r
	86	gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase\|0\|UINT32\|0x0000002A\r
	87	gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase\|0\|UINT32\|0x0000002B\r
	88	gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase\|0\|UINT32\|0x0000002C\r
	89	\r
	90	## SP805 Watchdog\r
	91	gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase\|0x0\|UINT32\|0x00000023\r
	92	gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz\|32000\|UINT32\|0x00000021\r
	93	\r
	94	## PL011 UART\r
	95	gArmPlatformTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth\|0x00000000\|UINT32\|0x0000001F\r
	96	gArmPlatformTokenSpaceGuid.PcdUartDefaultTimeout\|0x00000000\|UINT32\|0x00000020\r
	97	\r
	98	## PL031 RealTimeClock\r
	99	gArmPlatformTokenSpaceGuid.PcdPL031RtcBase\|0x0\|UINT32\|0x00000024\r
	100	gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy\|300000000\|UINT32\|0x00000022\r
	101	\r
	102	## PL061 GPIO\r
	103	gArmPlatformTokenSpaceGuid.PcdPL061GpioBase\|0x0\|UINT32\|0x00000025\r
	104	\r
	105	## PL111 Lcd\r
	106	gArmPlatformTokenSpaceGuid.PcdPL111LcdBase\|0x0\|UINT32\|0x00000026\r
	107	gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase\|0x0\|UINT32\|0x00000027\r
	108	\r
	109	## PL180 MCI\r
	110	gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress\|0x00000000\|UINT32\|0x00000028\r
	111	gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress\|0x00000000\|UINT32\|0x00000029\r
	112	\r
	113	#\r
	114	# BDS - Boot Manager\r
	115	#\r
	116	gArmPlatformTokenSpaceGuid.PcdFirmwareVendor\|"ARM Platform"\|VOID*\|0x00000019\r
	117	gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription\|L"Default Boot Device"\|VOID*\|0x0000000C\r
	118	gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath\|L""\|VOID*\|0x0000000D\r
	119	gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath\|L""\|VOID*\|0x0000000E\r
	120	gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument\|""\|VOID*\|0x000000F\r
	121	# PcdDefaultBootType define the type of the binary pointed by PcdDefaultBootDevicePath: \r
	122	# - 0 = an EFI application\r
	123	# - 1 = a Linux kernel with ATAG support\r
	124	# - 2 = a Linux kernel with FDT support\r
	125	gArmPlatformTokenSpaceGuid.PcdDefaultBootType\|0\|UINT32\|0x00000010\r
	126	gArmPlatformTokenSpaceGuid.PcdFdtDevicePath\|L""\|VOID*\|0x00000011\r
	127	\r
	128	## Timeout value for displaying progressing bar in before boot OS.\r
	129	# According to UEFI 2.0 spec, the default TimeOut should be 0xffff.\r
	130	gArmPlatformTokenSpaceGuid.PcdPlatformBootTimeOut\|0xffff\|UINT16\|0x0000001A\r
131	\r
132	gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths\|L""\|VOID*\|0x0000001B\r
133	gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths\|L""\|VOID*\|0x0000001C\r
134	\r