[mirror_edk2.git] / ArmPlatformPkg / ArmPlatformPkg.dec

#/** @file\r
#\r
#  Copyright (c) 2011-2017, ARM Limited. All rights reserved.\r
#  Copyright (c) 2015, Intel Corporation. All rights reserved.\r
#\r
#  This program and the accompanying materials\r
#  are licensed and made available under the terms and conditions of the BSD License\r
#  which accompanies this distribution.  The full text of the license may be found at\r
#  http://opensource.org/licenses/bsd-license.php\r
#\r
#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
#\r
#**/\r
\r
[Defines]\r
  DEC_SPECIFICATION              = 0x00010005\r
  PACKAGE_NAME                   = ArmPlatformPkg\r
  PACKAGE_GUID                   = 3308e0a0-1d94-11e0-915c-0002a5d5c51b\r
  PACKAGE_VERSION                = 0.1\r
\r
################################################################################\r
#\r
# Include Section - list of Include Paths that are provided by this package.\r
#                   Comments are used for Keywords and Module Types.\r
#\r
# Supported Module Types:\r
#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
#\r
################################################################################\r
[Includes.common]\r
  Include                        # Root include for the package\r
\r
[LibraryClasses]\r
  ArmPlatformLib|Include/Library/ArmPlatformLib.h\r
  LcdPlatformLib|Include/Library/LcdPlatformLib.h\r
  NorFlashPlatformLib|Include/Library/NorFlashPlatformLib.h\r
  PL011UartLib|Include/Library/PL011UartLib.h\r
\r
[Guids.common]\r
  gArmPlatformTokenSpaceGuid   = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }\r
  #\r
  # Following Guid must match FILE_GUID in MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf\r
  #\r
  gVariableRuntimeDxeFileGuid = { 0xcbd2e4d5, 0x7068, 0x4ff5, { 0xb4, 0x62, 0x98, 0x22, 0xb4, 0xad, 0x8d, 0x60 } }\r
\r
  gArmBootMonFsFileInfoGuid   = { 0x41e26b9c, 0xada6, 0x45b3, { 0x80, 0x8e, 0x23, 0x57, 0xa3, 0x5b, 0x60, 0xd6 } }\r
\r
[PcdsFeatureFlag.common]\r
  # Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0.\r
  gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping|FALSE|BOOLEAN|0x00000012\r
\r
  gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE|BOOLEAN|0x00000001\r
  gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004\r
\r
  gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked|FALSE|BOOLEAN|0x0000003C\r
\r
  # Disable the GOP controller on ExitBootServices(). By default the value is FALSE,\r
  # we assume the OS will handle the FrameBuffer from the UEFI GOP information.\r
  gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices|FALSE|BOOLEAN|0x0000003D\r
\r
  # Enable Legacy Linux support in the BDS\r
  gArmPlatformTokenSpaceGuid.PcdBdsLinuxSupport|FALSE|BOOLEAN|0x0000002E\r
\r
[PcdsFixedAtBuild.common]\r
  gArmPlatformTokenSpaceGuid.PcdCoreCount|1|UINT32|0x00000039\r
  gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038\r
\r
  # Stack for CPU Cores in Secure Mode\r
  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT64|0x00000005\r
  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000|UINT32|0x00000036\r
  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000|UINT32|0x00000006\r
\r
  # Stack for CPU Cores in Non Secure Mode\r
  gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT64|0x00000009\r
  gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037\r
  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000|UINT32|0x0000000A\r
\r
  # Size of the region used by UEFI in permanent memory (Reserved 128MB by default)\r
  gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015\r
\r
  # Boot Monitor FileSystem\r
  gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths|L""|VOID*|0x0000003A\r
\r
  #\r
  # ARM Primecells\r
  #\r
\r
  ## SP805 Watchdog\r
  gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0|UINT32|0x00000023\r
  gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|32000|UINT32|0x00000021\r
\r
  ## PL011 UART\r
  gArmPlatformTokenSpaceGuid.PL011UartClkInHz|24000000|UINT32|0x0000001F\r
  gArmPlatformTokenSpaceGuid.PL011UartInteger|0|UINT32|0x00000020\r
  gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D\r
  gArmPlatformTokenSpaceGuid.PL011UartInterrupt|0x00000000|UINT32|0x0000002F\r
  gArmPlatformTokenSpaceGuid.PL011UartRegOffsetVariant|0|UINT8|0x0000003E\r
\r
  ## PL011 Serial Debug UART\r
  gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x00000000|UINT64|0x00000030\r
  gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|0x00000000|UINT64|0x00000031\r
  gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz|0x00000000|UINT32|0x00000032\r
\r
  ## PL061 GPIO\r
  gArmPlatformTokenSpaceGuid.PcdPL061GpioBase|0x0|UINT32|0x00000025\r
\r
  ## PL111 Lcd & HdLcd\r
  gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026\r
  gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027\r
\r
  ## PL180 MCI\r
  gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x00000028\r
  gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00000029\r
\r
  #\r
  # BDS - Boot Manager\r
  #\r
  gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Platform"|VOID*|0x00000019\r
  gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Default Boot Device"|VOID*|0x0000000C\r
  gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L""|VOID*|0x0000000D\r
  gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|L""|VOID*|0x000000F\r
\r
  gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L""|VOID*|0x0000001B\r
  gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L""|VOID*|0x0000001C\r
\r
[PcdsFixedAtBuild.common,PcdsDynamic.common]\r
  ## PL031 RealTimeClock\r
  gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024\r
  gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022\r
\r
  gArmPlatformTokenSpaceGuid.PcdWatchdogCount|0x0|UINT32|0x00000033\r
\r
[PcdsFixedAtBuild.ARM]\r
  # Stack for CPU Cores in Secure Monitor Mode\r
  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT64|0x00000007\r
  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000|UINT32|0x00000008\r
\r
[PcdsFixedAtBuild.AARCH64]\r
  # The Secure World is only running in EL3. Only one set of stacks is needed for AArch64.\r
  # The Secure stacks are described by PcdCPUCoresSecStackBase, PcdCPUCoreSecPrimaryStackSize\r
  # and PcdCPUCoreSecSecondaryStackSize\r
  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT64|0x00000007\r
  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x0|UINT32|0x00000008\r
\r
Commit	Line	Data
11c20f4e	1	#/** @file\r
11c20f4e	2	#\r
08e94eee	3	# Copyright (c) 2011-2017, ARM Limited. All rights reserved.\r
ad7a56e5	4	# Copyright (c) 2015, Intel Corporation. All rights reserved.\r
11c20f4e	5	#\r
3402aac7 RC	6	# This program and the accompanying materials\r
	7	# are licensed and made available under the terms and conditions of the BSD License\r
	8	# which accompanies this distribution. The full text of the license may be found at\r
	9	# http://opensource.org/licenses/bsd-license.php\r
	10	#\r
	11	# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
11c20f4e	13	#\r
	14	#**/\r
	15	\r
	16	[Defines]\r
	17	DEC_SPECIFICATION = 0x00010005\r
	18	PACKAGE_NAME = ArmPlatformPkg\r
3402aac7	19	PACKAGE_GUID = 3308e0a0-1d94-11e0-915c-0002a5d5c51b\r
11c20f4e	20	PACKAGE_VERSION = 0.1\r
	21	\r
	22	################################################################################\r
	23	#\r
	24	# Include Section - list of Include Paths that are provided by this package.\r
	25	# Comments are used for Keywords and Module Types.\r
	26	#\r
	27	# Supported Module Types:\r
	28	# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
	29	#\r
	30	################################################################################\r
	31	[Includes.common]\r
	32	Include # Root include for the package\r
	33	\r
12156134	34	[LibraryClasses]\r
d9b53608 AB	35	ArmPlatformLib\|Include/Library/ArmPlatformLib.h\r
	36	LcdPlatformLib\|Include/Library/LcdPlatformLib.h\r
	37	NorFlashPlatformLib\|Include/Library/NorFlashPlatformLib.h\r
12156134 AB	38	PL011UartLib\|Include/Library/PL011UartLib.h\r
12156134 AB	39	\r
11c20f4e	40	[Guids.common]\r
	41	gArmPlatformTokenSpaceGuid = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }\r
	42	#\r
	43	# Following Guid must match FILE_GUID in MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf\r
	44	#\r
	45	gVariableRuntimeDxeFileGuid = { 0xcbd2e4d5, 0x7068, 0x4ff5, { 0xb4, 0x62, 0x98, 0x22, 0xb4, 0xad, 0x8d, 0x60 } }\r
	46	\r
da5daf36 HL	47	gArmBootMonFsFileInfoGuid = { 0x41e26b9c, 0xada6, 0x45b3, { 0x80, 0x8e, 0x23, 0x57, 0xa3, 0x5b, 0x60, 0xd6 } }\r
da5daf36 HL	48	\r
11c20f4e	49	[PcdsFeatureFlag.common]\r
	50	# Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0.\r
	51	gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping\|FALSE\|BOOLEAN\|0x00000012\r
3402aac7	52	\r
11c20f4e	53	gArmPlatformTokenSpaceGuid.PcdStandalone\|TRUE\|BOOLEAN\|0x00000001\r
11c20f4e	54	gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores\|FALSE\|BOOLEAN\|0x00000004\r
11c20f4e	55	\r
68dda854	56	gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked\|FALSE\|BOOLEAN\|0x0000003C\r
d8c4bb9a OM	57	\r
	58	# Disable the GOP controller on ExitBootServices(). By default the value is FALSE,\r
	59	# we assume the OS will handle the FrameBuffer from the UEFI GOP information.\r
	60	gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices\|FALSE\|BOOLEAN\|0x0000003D\r
	61	\r
5d9e9d1a	62	# Enable Legacy Linux support in the BDS\r
afd6b289	63	gArmPlatformTokenSpaceGuid.PcdBdsLinuxSupport\|FALSE\|BOOLEAN\|0x0000002E\r
5d9e9d1a	64	\r
11c20f4e	65	[PcdsFixedAtBuild.common]\r
695df8ba	66	gArmPlatformTokenSpaceGuid.PcdCoreCount\|1\|UINT32\|0x00000039\r
2dbcb8f0	67	gArmPlatformTokenSpaceGuid.PcdClusterCount\|1\|UINT32\|0x00000038\r
3402aac7	68	\r
11c20f4e	69	# Stack for CPU Cores in Secure Mode\r
91673dfd	70	gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase\|0\|UINT64\|0x00000005\r
2dbcb8f0	71	gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize\|0x10000\|UINT32\|0x00000036\r
2dbcb8f0	72	gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize\|0x1000\|UINT32\|0x00000006\r
11c20f4e	73	\r
11c20f4e	74	# Stack for CPU Cores in Non Secure Mode\r
bb5420bb	75	gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase\|0\|UINT64\|0x00000009\r
2dbcb8f0	76	gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize\|0x10000\|UINT32\|0x00000037\r
2dbcb8f0	77	gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize\|0x1000\|UINT32\|0x0000000A\r
3402aac7	78	\r
11c20f4e	79	# Size of the region used by UEFI in permanent memory (Reserved 128MB by default)\r
	80	gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize\|0x08000000\|UINT32\|0x00000015\r
	81	\r
94e0955d OM	82	# Boot Monitor FileSystem\r
	83	gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths\|L""\|VOID*\|0x0000003A\r
	84	\r
11c20f4e	85	#\r
	86	# ARM Primecells\r
	87	#\r
	88	\r
11c20f4e	89	## SP805 Watchdog\r
	90	gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase\|0x0\|UINT32\|0x00000023\r
	91	gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz\|32000\|UINT32\|0x00000021\r
	92	\r
	93	## PL011 UART\r
051e63bb	94	gArmPlatformTokenSpaceGuid.PL011UartClkInHz\|24000000\|UINT32\|0x0000001F\r
	95	gArmPlatformTokenSpaceGuid.PL011UartInteger\|0\|UINT32\|0x00000020\r
	96	gArmPlatformTokenSpaceGuid.PL011UartFractional\|0\|UINT32\|0x0000002D\r
7dfe9309	97	gArmPlatformTokenSpaceGuid.PL011UartInterrupt\|0x00000000\|UINT32\|0x0000002F\r
d4f6c35c	98	gArmPlatformTokenSpaceGuid.PL011UartRegOffsetVariant\|0\|UINT8\|0x0000003E\r
11c20f4e	99	\r
0312b14d EL	100	## PL011 Serial Debug UART\r
	101	gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase\|0x00000000\|UINT64\|0x00000030\r
	102	gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate\|0x00000000\|UINT64\|0x00000031\r
	103	gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz\|0x00000000\|UINT32\|0x00000032\r
	104	\r
11c20f4e	105	## PL061 GPIO\r
11c20f4e	106	gArmPlatformTokenSpaceGuid.PcdPL061GpioBase\|0x0\|UINT32\|0x00000025\r
3402aac7	107	\r
98622390	108	## PL111 Lcd & HdLcd\r
11c20f4e	109	gArmPlatformTokenSpaceGuid.PcdPL111LcdBase\|0x0\|UINT32\|0x00000026\r
11c20f4e	110	gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase\|0x0\|UINT32\|0x00000027\r
3402aac7	111	\r
11c20f4e	112	## PL180 MCI\r
	113	gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress\|0x00000000\|UINT32\|0x00000028\r
	114	gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress\|0x00000000\|UINT32\|0x00000029\r
	115	\r
	116	#\r
	117	# BDS - Boot Manager\r
	118	#\r
	119	gArmPlatformTokenSpaceGuid.PcdFirmwareVendor\|"ARM Platform"\|VOID*\|0x00000019\r
	120	gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription\|L"Default Boot Device"\|VOID*\|0x0000000C\r
	121	gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath\|L""\|VOID*\|0x0000000D\r
6bcedcec	122	gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument\|L""\|VOID*\|0x000000F\r
3402aac7	123	\r
11c20f4e	124	gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths\|L""\|VOID*\|0x0000001B\r
11c20f4e	125	gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths\|L""\|VOID*\|0x0000001C\r
1bc83266	126	\r
b4e2799b AB	127	[PcdsFixedAtBuild.common,PcdsDynamic.common]\r
	128	## PL031 RealTimeClock\r
	129	gArmPlatformTokenSpaceGuid.PcdPL031RtcBase\|0x0\|UINT32\|0x00000024\r
	130	gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy\|300000000\|UINT32\|0x00000022\r
	131	\r
08e94eee SM	132	gArmPlatformTokenSpaceGuid.PcdWatchdogCount\|0x0\|UINT32\|0x00000033\r
08e94eee SM	133	\r
1bc83266 HL	134	[PcdsFixedAtBuild.ARM]\r
1bc83266 HL	135	# Stack for CPU Cores in Secure Monitor Mode\r
91673dfd	136	gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase\|0\|UINT64\|0x00000007\r
1bc83266 HL	137	gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize\|0x1000\|UINT32\|0x00000008\r
	138	\r
	139	[PcdsFixedAtBuild.AARCH64]\r
	140	# The Secure World is only running in EL3. Only one set of stacks is needed for AArch64.\r
	141	# The Secure stacks are described by PcdCPUCoresSecStackBase, PcdCPUCoreSecPrimaryStackSize\r
	142	# and PcdCPUCoreSecSecondaryStackSize\r
91673dfd	143	gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase\|0\|UINT64\|0x00000007\r
1bc83266 HL	144	gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize\|0x0\|UINT32\|0x00000008\r
1bc83266 HL	145	\r