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[mirror_edk2.git] / ArmPlatformPkg / ArmRealViewEbPkg / Include / Platform / ArmPlatform.h

/** @file\r
*  Header defining RealView EB constants (Base addresses, sizes, flags)\r
*\r
*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
*\r
*  This program and the accompanying materials\r
*  are licensed and made available under the terms and conditions of the BSD License\r
*  which accompanies this distribution.  The full text of the license may be found at\r
*  http://opensource.org/licenses/bsd-license.php\r
*\r
*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
*\r
**/\r
\r
#ifndef __ARM_EB_H__\r
#define __ARM_EB_H__\r
\r
/*******************************************\r
// Platform Memory Map\r
*******************************************/\r
\r
// Can be NOR, DOC, DRAM, SRAM\r
#define ARM_EB_REMAP_BASE                     0x00000000\r
#define ARM_EB_REMAP_SZ                       0x04000000\r
\r
// Motherboard Peripheral and On-chip peripheral\r
#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE     0x10000000\r
#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_SZ       0x10000000\r
#define ARM_EB_BOARD_PERIPH_BASE              0x10000000\r
//#define ARM_EB_CHIP_PERIPH_BASE             0x10020000\r
\r
// SMC\r
#define ARM_EB_SMC_BASE                       0x40000000\r
#define ARM_EB_SMC_SZ                         0x20000000\r
\r
// NOR Flash 1\r
#define ARM_EB_SMB_NOR_BASE                   0x40000000\r
#define ARM_EB_SMB_NOR_SZ                     0x04000000 /* 64 MB */\r
// DOC Flash\r
#define ARM_EB_SMB_DOC_BASE                   0x44000000\r
#define ARM_EB_SMB_DOC_SZ                     0x04000000 /* 64 MB */\r
// SRAM\r
#define ARM_EB_SMB_SRAM_BASE                  0x48000000\r
#define ARM_EB_SMB_SRAM_SZ                    0x02000000 /* 32 MB */\r
// USB, Ethernet, VRAM\r
#define ARM_EB_SMB_PERIPH_BASE                0x4E000000\r
//#define ARM_EB_SMB_PERIPH_VRAM              0x4C000000\r
#define ARM_EB_SMB_PERIPH_SZ                  0x02000000 /* 32 MB */\r
\r
// Logic Tile\r
#define ARM_EB_LOGIC_TILE_BASE                0xC0000000\r
#define ARM_EB_LOGIC_TILE_SZ                  0x40000000\r
\r
/*******************************************\r
// Motherboard peripherals\r
*******************************************/\r
\r
// Define MotherBoard SYS flags offsets (from ARM_EB_BOARD_PERIPH_BASE)\r
#define ARM_EB_SYS_ID_REG                     (ARM_EB_BOARD_PERIPH_BASE + 0x00000)\r
#define ARM_EB_SYS_OSC4_REG                   (ARM_EB_BOARD_PERIPH_BASE + 0x0001C)\r
#define ARM_EB_SYS_LOCK_REG                   (ARM_EB_BOARD_PERIPH_BASE + 0x00020)\r
#define ARM_EB_SYS_100HZ_REG                  (ARM_EB_BOARD_PERIPH_BASE + 0x00024)\r
#define ARM_EB_SYS_FLAGS_REG                  (ARM_EB_BOARD_PERIPH_BASE + 0x00030)\r
#define ARM_EB_SYS_FLAGS_SET_REG              (ARM_EB_BOARD_PERIPH_BASE + 0x00030)\r
#define ARM_EB_SYS_FLAGS_CLR_REG              (ARM_EB_BOARD_PERIPH_BASE + 0x00034)\r
#define ARM_EB_SYS_FLAGS_NV_REG               (ARM_EB_BOARD_PERIPH_BASE + 0x00038)\r
#define ARM_EB_SYS_FLAGS_NV_SET_REG           (ARM_EB_BOARD_PERIPH_BASE + 0x00038)\r
#define ARM_EB_SYS_FLAGS_NV_CLR_REG           (ARM_EB_BOARD_PERIPH_BASE + 0x0003C)\r
#define ARM_EB_SYS_RESETCTL_REG               (ARM_EB_BOARD_PERIPH_BASE + 0x00040)\r
#define ARM_EB_SYS_CLCD_REG                   (ARM_EB_BOARD_PERIPH_BASE + 0x00050)\r
#define ARM_EB_SYS_PROCID0_REG                (ARM_EB_BOARD_PERIPH_BASE + 0x00084)\r
#define ARM_EB_SYS_PROCID1_REG                (ARM_EB_BOARD_PERIPH_BASE + 0x00088)\r
\r
// SP810 Controller\r
#define SP810_CTRL_BASE                       (ARM_EB_BOARD_PERIPH_BASE + 0x01000)\r
\r
// SYSTRCL Register\r
#define ARM_EB_SYSCTRL                        0x10001000\r
\r
// Dynamic Memory Controller Base\r
#define ARM_EB_DMC_BASE                       0x10018000\r
\r
// Static Memory Controller Base\r
#define ARM_EB_SMC_CTRL_BASE                  0x10080000\r
\r
//Note: Moving the framebuffer into the 0x70000000-0x80000000 region does not seem to work\r
#define PL111_CLCD_VRAM_BASE                  0x00100000\r
\r
/*// System Configuration Controller register Base addresses\r
//#define ARM_EB_SYS_CFG_CTRL_BASE                0x100E2000\r
#define ARM_EB_SYS_CFGRW0_REG                   0x100E2000\r
#define ARM_EB_SYS_CFGRW1_REG                   0x100E2004\r
#define ARM_EB_SYS_CFGRW2_REG                   0x100E2008\r
\r
#define ARM_EB_CFGRW1_REMAP_NOR0                0\r
#define ARM_EB_CFGRW1_REMAP_NOR1                (1 << 28)\r
#define ARM_EB_CFGRW1_REMAP_EXT_AXI             (1 << 29)\r
#define ARM_EB_CFGRW1_REMAP_DRAM                (1 << 30)\r
\r
// PL301 Fast AXI Base Address\r
#define ARM_EB_FAXI_BASE                        0x100E9000\r
\r
// L2x0 Cache Controller Base Address\r
//#define ARM_EB_L2x0_CTLR_BASE                   0x1E00A000*/\r
\r
#define ARM_EB_SYS_PROC_ID_MASK                  (UINT32)(0xFFU << 24)\r
#define ARM_EB_SYS_PROC_ID_CORTEX_A8             (UINT32)(0x0EU << 24)\r
#define ARM_EB_SYS_PROC_ID_CORTEX_A9             (UINT32)(0x0CU << 24)\r
\r
/*******************************************\r
// System Configuration Control\r
*******************************************/\r
\r
// Sites where the peripheral is fitted\r
#define ARM_EB_UNSUPPORTED                        ~0\r
\r
#define VIRTUAL_SYS_CFG(site,func)                     (((site) << 24) | (func))\r
\r
#define SYS_CFG_RTC                               VIRTUAL_SYS_CFG(ARM_EB_UNSUPPORTED,1)\r
\r
#endif\r