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1d5d0ae9 | 1 | /** @file |
2 | * | |
f437141a | 3 | * Copyright (c) 2011-2012, ARM Limited. All rights reserved. |
1d5d0ae9 | 4 | * |
5 | * This program and the accompanying materials | |
6 | * are licensed and made available under the terms and conditions of the BSD License | |
7 | * which accompanies this distribution. The full text of the license may be found at | |
8 | * http://opensource.org/licenses/bsd-license.php | |
9 | * | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
12 | * | |
13 | **/ | |
14 | ||
15 | #include <Library/IoLib.h> | |
f437141a | 16 | #include <Library/ArmLib.h> |
1d5d0ae9 | 17 | #include <Library/ArmPlatformLib.h> |
18 | #include <Library/DebugLib.h> | |
19 | #include <Library/PcdLib.h> | |
23792dea | 20 | |
1d5d0ae9 | 21 | #include <Drivers/PL341Dmc.h> |
23792dea | 22 | #include <Drivers/SP804Timer.h> |
1d5d0ae9 | 23 | |
44788bae | 24 | #include <Ppi/ArmMpCoreInfo.h> |
25 | ||
5cc45b70 | 26 | #include <ArmPlatform.h> |
27 | ||
44788bae | 28 | ARM_CORE_INFO mRealViewEbMpCoreInfoTable[] = { |
29 | { | |
30 | // Cluster 0, Core 0 | |
31 | 0x0, 0x0, | |
32 | ||
33 | // MP Core MailBox Set/Get/Clear Addresses and Clear Value | |
34 | (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_REG, | |
35 | (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_SET_REG, | |
36 | (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_CLR_REG, | |
37 | (UINT64)0xFFFFFFFF | |
38 | }, | |
39 | { | |
40 | // Cluster 0, Core 1 | |
41 | 0x0, 0x1, | |
42 | ||
43 | // MP Core MailBox Set/Get/Clear Addresses and Clear Value | |
44 | (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_REG, | |
45 | (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_SET_REG, | |
46 | (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_CLR_REG, | |
47 | (UINT64)0xFFFFFFFF | |
48 | } | |
49 | }; | |
50 | ||
a534d714 | 51 | /** |
52 | Return the current Boot Mode | |
53 | ||
54 | This function returns the boot reason on the platform | |
55 | ||
56 | **/ | |
57 | EFI_BOOT_MODE | |
58 | ArmPlatformGetBootMode ( | |
59 | VOID | |
60 | ) | |
61 | { | |
62 | return BOOT_WITH_FULL_CONFIGURATION; | |
63 | } | |
64 | ||
aa01abaa | 65 | /** |
66 | Initialize controllers that must setup in the normal world | |
67 | ||
5cc45b70 | 68 | This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei |
aa01abaa | 69 | in the PEI phase. |
70 | ||
71 | **/ | |
f437141a | 72 | RETURN_STATUS |
73 | ArmPlatformInitialize ( | |
74 | IN UINTN MpId | |
aa01abaa | 75 | ) |
76 | { | |
f437141a | 77 | if (!IS_PRIMARY_CORE(MpId)) { |
78 | return RETURN_SUCCESS; | |
79 | } | |
80 | ||
8d0fe26c | 81 | // Disable memory remapping and return to normal mapping |
82 | MmioOr32 (ARM_EB_SYSCTRL, BIT8); //EB_SP810_CTRL_BASE | |
83 | ||
23792dea | 84 | // Configure periodic timer (TIMER0) for 1MHz operation |
85 | MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK); | |
86 | // Configure 1MHz clock | |
87 | MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK); | |
88 | // configure SP810 to use 1MHz clock and disable | |
89 | MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK); | |
90 | // Configure SP810 to use 1MHz clock and disable | |
91 | MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK); | |
f437141a | 92 | |
93 | return RETURN_SUCCESS; | |
aa01abaa | 94 | } |
95 | ||
1d5d0ae9 | 96 | /** |
97 | Initialize the system (or sometimes called permanent) memory | |
98 | ||
99 | This memory is generally represented by the DRAM. | |
100 | ||
101 | **/ | |
aa01abaa | 102 | VOID |
103 | ArmPlatformInitializeSystemMemory ( | |
104 | VOID | |
105 | ) | |
106 | { | |
107 | // We do not need to initialize the System Memory on RTSM | |
1d5d0ae9 | 108 | } |
44788bae | 109 | |
110 | EFI_STATUS | |
111 | PrePeiCoreGetMpCoreInfo ( | |
112 | OUT UINTN *CoreCount, | |
113 | OUT ARM_CORE_INFO **ArmCoreTable | |
114 | ) | |
115 | { | |
116 | if ((MmioRead32 (ARM_EB_SYS_PROCID0_REG) & ARM_EB_SYS_PROC_ID_MASK) == ARM_EB_SYS_PROC_ID_CORTEX_A9) { | |
117 | *CoreCount = sizeof(mRealViewEbMpCoreInfoTable) / sizeof(ARM_CORE_INFO); | |
118 | *ArmCoreTable = mRealViewEbMpCoreInfoTable; | |
119 | return EFI_SUCCESS; | |
120 | } else { | |
121 | return EFI_UNSUPPORTED; | |
122 | } | |
123 | } | |
124 | ||
125 | // Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore | |
126 | EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID; | |
127 | ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo }; | |
128 | ||
129 | EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { | |
130 | { | |
131 | EFI_PEI_PPI_DESCRIPTOR_PPI, | |
132 | &mArmMpCoreInfoPpiGuid, | |
133 | &mMpCoreInfoPpi | |
134 | } | |
135 | }; | |
136 | ||
77de7e53 | 137 | VOID |
138 | ArmPlatformGetPlatformPpiList ( | |
139 | OUT UINTN *PpiListSize, | |
140 | OUT EFI_PEI_PPI_DESCRIPTOR **PpiList | |
141 | ) | |
142 | { | |
44788bae | 143 | *PpiListSize = sizeof(gPlatformPpiTable); |
144 | *PpiList = gPlatformPpiTable; | |
77de7e53 | 145 | } |
146 |