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1d5d0ae9 | 1 | /** @file |
2 | * | |
3 | * Copyright (c) 2011, ARM Limited. All rights reserved. | |
4 | * | |
5 | * This program and the accompanying materials | |
6 | * are licensed and made available under the terms and conditions of the BSD License | |
7 | * which accompanies this distribution. The full text of the license may be found at | |
8 | * http://opensource.org/licenses/bsd-license.php | |
9 | * | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
12 | * | |
13 | **/ | |
14 | ||
15 | #include <Library/IoLib.h> | |
16 | #include <Library/ArmPlatformLib.h> | |
17 | #include <Library/DebugLib.h> | |
18 | #include <Library/PcdLib.h> | |
23792dea | 19 | |
1d5d0ae9 | 20 | #include <Drivers/PL341Dmc.h> |
23792dea | 21 | #include <Drivers/SP804Timer.h> |
1d5d0ae9 | 22 | |
44788bae | 23 | #include <Ppi/ArmMpCoreInfo.h> |
24 | ||
5cc45b70 | 25 | #include <ArmPlatform.h> |
26 | ||
44788bae | 27 | ARM_CORE_INFO mRealViewEbMpCoreInfoTable[] = { |
28 | { | |
29 | // Cluster 0, Core 0 | |
30 | 0x0, 0x0, | |
31 | ||
32 | // MP Core MailBox Set/Get/Clear Addresses and Clear Value | |
33 | (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_REG, | |
34 | (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_SET_REG, | |
35 | (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_CLR_REG, | |
36 | (UINT64)0xFFFFFFFF | |
37 | }, | |
38 | { | |
39 | // Cluster 0, Core 1 | |
40 | 0x0, 0x1, | |
41 | ||
42 | // MP Core MailBox Set/Get/Clear Addresses and Clear Value | |
43 | (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_REG, | |
44 | (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_SET_REG, | |
45 | (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_CLR_REG, | |
46 | (UINT64)0xFFFFFFFF | |
47 | } | |
48 | }; | |
49 | ||
1d5d0ae9 | 50 | /** |
51 | Remap the memory at 0x0 | |
52 | ||
53 | Some platform requires or gives the ability to remap the memory at the address 0x0. | |
54 | This function can do nothing if this feature is not relevant to your platform. | |
55 | ||
56 | **/ | |
aa01abaa | 57 | VOID |
58 | ArmPlatformBootRemapping ( | |
59 | VOID | |
60 | ) | |
61 | { | |
1d5d0ae9 | 62 | // Disable memory remapping and return to normal mapping |
aa01abaa | 63 | MmioOr32 (ARM_EB_SYSCTRL, BIT8); //EB_SP810_CTRL_BASE |
1d5d0ae9 | 64 | } |
65 | ||
a534d714 | 66 | /** |
67 | Return the current Boot Mode | |
68 | ||
69 | This function returns the boot reason on the platform | |
70 | ||
71 | **/ | |
72 | EFI_BOOT_MODE | |
73 | ArmPlatformGetBootMode ( | |
74 | VOID | |
75 | ) | |
76 | { | |
77 | return BOOT_WITH_FULL_CONFIGURATION; | |
78 | } | |
79 | ||
aa01abaa | 80 | /** |
81 | Initialize controllers that must setup in the normal world | |
82 | ||
5cc45b70 | 83 | This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei |
aa01abaa | 84 | in the PEI phase. |
85 | ||
86 | **/ | |
87 | VOID | |
88 | ArmPlatformNormalInitialize ( | |
89 | VOID | |
90 | ) | |
91 | { | |
23792dea | 92 | // Configure periodic timer (TIMER0) for 1MHz operation |
93 | MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK); | |
94 | // Configure 1MHz clock | |
95 | MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK); | |
96 | // configure SP810 to use 1MHz clock and disable | |
97 | MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK); | |
98 | // Configure SP810 to use 1MHz clock and disable | |
99 | MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK); | |
aa01abaa | 100 | } |
101 | ||
1d5d0ae9 | 102 | /** |
103 | Initialize the system (or sometimes called permanent) memory | |
104 | ||
105 | This memory is generally represented by the DRAM. | |
106 | ||
107 | **/ | |
aa01abaa | 108 | VOID |
109 | ArmPlatformInitializeSystemMemory ( | |
110 | VOID | |
111 | ) | |
112 | { | |
113 | // We do not need to initialize the System Memory on RTSM | |
1d5d0ae9 | 114 | } |
44788bae | 115 | |
116 | EFI_STATUS | |
117 | PrePeiCoreGetMpCoreInfo ( | |
118 | OUT UINTN *CoreCount, | |
119 | OUT ARM_CORE_INFO **ArmCoreTable | |
120 | ) | |
121 | { | |
122 | if ((MmioRead32 (ARM_EB_SYS_PROCID0_REG) & ARM_EB_SYS_PROC_ID_MASK) == ARM_EB_SYS_PROC_ID_CORTEX_A9) { | |
123 | *CoreCount = sizeof(mRealViewEbMpCoreInfoTable) / sizeof(ARM_CORE_INFO); | |
124 | *ArmCoreTable = mRealViewEbMpCoreInfoTable; | |
125 | return EFI_SUCCESS; | |
126 | } else { | |
127 | return EFI_UNSUPPORTED; | |
128 | } | |
129 | } | |
130 | ||
131 | // Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore | |
132 | EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID; | |
133 | ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo }; | |
134 | ||
135 | EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { | |
136 | { | |
137 | EFI_PEI_PPI_DESCRIPTOR_PPI, | |
138 | &mArmMpCoreInfoPpiGuid, | |
139 | &mMpCoreInfoPpi | |
140 | } | |
141 | }; | |
142 | ||
77de7e53 | 143 | VOID |
144 | ArmPlatformGetPlatformPpiList ( | |
145 | OUT UINTN *PpiListSize, | |
146 | OUT EFI_PEI_PPI_DESCRIPTOR **PpiList | |
147 | ) | |
148 | { | |
44788bae | 149 | *PpiListSize = sizeof(gPlatformPpiTable); |
150 | *PpiList = gPlatformPpiTable; | |
77de7e53 | 151 | } |
152 |