[mirror_edk2.git] / ArmPlatformPkg / ArmVExpressPkg / Include / Platform / CTA9x4 / ArmPlatform.h

/** @file\r
*  Header defining Versatile Express constants (Base addresses, sizes, flags)\r
*\r
*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
*\r
*  This program and the accompanying materials\r
*  are licensed and made available under the terms and conditions of the BSD License\r
*  which accompanies this distribution.  The full text of the license may be found at\r
*  http://opensource.org/licenses/bsd-license.php\r
*\r
*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
*\r
**/\r
\r
#ifndef __ARM_VEXPRESS_H__\r
#define __ARM_VEXPRESS_H__\r
\r
#include <Base.h>\r
#include <VExpressMotherBoard.h>\r
\r
/***********************************************************************************\r
// Platform Memory Map\r
************************************************************************************/\r
\r
// Can be NOR0, NOR1, DRAM\r
#define ARM_VE_REMAP_BASE                       0x00000000\r
#define ARM_VE_REMAP_SZ                         SIZE_64MB\r
\r
// Motherboard Peripheral and On-chip peripheral\r
#define ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE       0x10000000\r
#define ARM_VE_SMB_MB_ON_CHIP_PERIPH_SZ         SIZE_256MB\r
#define ARM_VE_BOARD_PERIPH_BASE                0x10000000\r
#define ARM_VE_CHIP_PERIPH_BASE                 0x10020000\r
\r
// SMC\r
#define ARM_VE_SMC_BASE                         0x40000000\r
#define ARM_VE_SMC_SZ                           0x1C000000\r
\r
// NOR Flash 1\r
#define ARM_VE_SMB_NOR0_BASE                    0x40000000\r
#define ARM_VE_SMB_NOR0_SZ                      SIZE_64MB\r
// NOR Flash 2\r
#define ARM_VE_SMB_NOR1_BASE                    0x44000000\r
#define ARM_VE_SMB_NOR1_SZ                      SIZE_64MB\r
// SRAM\r
#define ARM_VE_SMB_SRAM_BASE                    0x48000000\r
#define ARM_VE_SMB_SRAM_SZ                      SIZE_32MB\r
// USB, Ethernet, VRAM\r
#define ARM_VE_SMB_PERIPH_BASE                  0x4C000000\r
#define PL111_CLCD_VRAM_MOTHERBOARD_BASE        ARM_VE_SMB_PERIPH_BASE\r
#define ARM_VE_SMB_PERIPH_SZ                    SIZE_64MB\r
\r
// DRAM\r
#define ARM_VE_DRAM_BASE                        0x60000000\r
#define ARM_VE_DRAM_SZ                          0x40000000\r
// Inside the DRAM we allocate a section for the VRAM (Video RAM)\r
#define LCD_VRAM_CORE_TILE_BASE                 0x64000000\r
\r
// External AXI between daughterboards (Logic Tile)\r
#define ARM_VE_EXT_AXI_BASE                     0xE0000000\r
#define ARM_VE_EXT_AXI_SZ                       0x20000000  /* 512 MB */\r
\r
\r
/***********************************************************************************\r
   Core Tile memory-mapped Peripherals\r
************************************************************************************/\r
\r
// PL111 Colour LCD Controller - core tile\r
#define PL111_CLCD_CORE_TILE_BASE               (ARM_VE_BOARD_PERIPH_BASE + 0x20000)\r
\r
// PL341 Dynamic Memory Controller Base\r
#define ARM_VE_DMC_BASE                         (ARM_VE_BOARD_PERIPH_BASE + 0xE0000)\r
\r
// PL354 Static Memory Controller Base\r
#define ARM_VE_SMC_CTRL_BASE                    (ARM_VE_BOARD_PERIPH_BASE + 0xE1000)\r
\r
// System Configuration Controller register Base addresses\r
//#define ARM_VE_SYS_CFG_CTRL_BASE              (ARM_VE_BOARD_PERIPH_BASE + 0xE2000)\r
#define ARM_VE_SYS_CFGRW0_REG                   (ARM_VE_BOARD_PERIPH_BASE + 0xE2000)\r
#define ARM_VE_SYS_CFGRW1_REG                   (ARM_VE_BOARD_PERIPH_BASE + 0xE2004)\r
#define ARM_VE_SYS_CFGRW2_REG                   (ARM_VE_BOARD_PERIPH_BASE + 0xE2008)\r
\r
#define ARM_PLATFORM_SCC_BASE                   ARM_VE_SYS_CFGRW0_REG\r
\r
// SP805 Watchdog on Cortex A9 core tile\r
#define SP805_WDOG_CORE_TILE_BASE               (ARM_VE_BOARD_PERIPH_BASE + 0xE5000)\r
\r
// BP147 TZPC Base Address\r
#define ARM_VE_TZPC_BASE                        (ARM_VE_BOARD_PERIPH_BASE + 0xE6000)\r
\r
// PL301 Fast AXI Base Address\r
#define ARM_VE_FAXI_BASE                        (ARM_VE_BOARD_PERIPH_BASE + 0xE9000)\r
\r
// TZASC Trust Zone Address Space Controller Base Address\r
#define ARM_VE_TZASC_BASE                       (ARM_VE_BOARD_PERIPH_BASE + 0xEC000)\r
\r
// PL310 L2x0 Cache Controller Base Address\r
//#define ARM_VE_L2x0_CTLR_BASE                 0x1E00A000\r
\r
/***********************************************************************************\r
   Select between Motherboard and Core Tile peripherals\r
************************************************************************************/\r
\r
// Specify which PL111 to use\r
//#define PL111_CLCD_BASE                       PL111_CLCD_MOTHERBOARD_BASE\r
#define PL111_CLCD_BASE                         PL111_CLCD_CORE_TILE_BASE\r
\r
/***********************************************************************************\r
   Peripherals' misc settings\r
************************************************************************************/\r
\r
#define ARM_VE_CFGRW1_TZASC_EN_BIT_MASK         0x2000\r
#define ARM_VE_CFGRW1_REMAP_NOR0                0\r
#define ARM_VE_CFGRW1_REMAP_NOR1                (1 << 28)\r
#define ARM_VE_CFGRW1_REMAP_EXT_AXI             (1 << 29)\r
#define ARM_VE_CFGRW1_REMAP_DRAM                (1 << 30)\r
\r
// TZASC - Other settings\r
#define ARM_VE_DECPROT_BIT_TZPC                 (1 << 6)\r
#define ARM_VE_DECPROT_BIT_DMC_TZASC            (1 << 11)\r
#define ARM_VE_DECPROT_BIT_NMC_TZASC            (1 << 12)\r
#define ARM_VE_DECPROT_BIT_SMC_TZASC            (1 << 13)\r
#define ARM_VE_DECPROT_BIT_EXT_MAST_TZ          (1)\r
#define ARM_VE_DECPROT_BIT_DMC_TZASC_LOCK       (1 << 3)\r
#define ARM_VE_DECPROT_BIT_NMC_TZASC_LOCK       (1 << 4)\r
#define ARM_VE_DECPROT_BIT_SMC_TZASC_LOCK       (1 << 5)\r
\r
\r
// PL111 Lcd\r
#define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID  1\r
\r
/***********************************************************************************\r
// Interrupt Map\r
************************************************************************************/\r
\r
// Timer Interrupts\r
#define TIMER01_INTERRUPT_NUM                   34\r
#define TIMER23_INTERRUPT_NUM                   35\r
\r
\r
/***********************************************************************************\r
// EFI Memory Map in Permanent Memory (DRAM)\r
************************************************************************************/\r
\r
// This region is allocated at the bottom of the DRAM. It will be used\r
// for fixed address allocations such as Vector Table\r
#define ARM_VE_EFI_FIX_ADDRESS_REGION_SZ        SIZE_8MB\r
\r
// This region is the memory declared to PEI as permanent memory for PEI\r
// and DXE. EFI stacks and heaps will be declared in this region.\r
#define ARM_VE_EFI_MEMORY_REGION_SZ             SIZE_256MB\r
\r
#endif\r
Commit	Line	Data
1d5d0ae9	1	/** @file\r
	2	* Header defining Versatile Express constants (Base addresses, sizes, flags)\r
	3	*\r
	4	* Copyright (c) 2011, ARM Limited. All rights reserved.\r
1d5d0ae9	5	*\r
76bc1743	6	* This program and the accompanying materials\r
	7	* are licensed and made available under the terms and conditions of the BSD License\r
	8	* which accompanies this distribution. The full text of the license may be found at\r
	9	* http://opensource.org/licenses/bsd-license.php\r
	10	*\r
	11	* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
1d5d0ae9	13	*\r
	14	**/\r
	15	\r
	16	#ifndef __ARM_VEXPRESS_H__\r
	17	#define __ARM_VEXPRESS_H__\r
	18	\r
76bc1743	19	#include <Base.h>\r
	20	#include <VExpressMotherBoard.h>\r
	21	\r
	22	/***********************************************************************************\r
1d5d0ae9	23	// Platform Memory Map\r
76bc1743	24	************************************************************************************/\r
1d5d0ae9	25	\r
	26	// Can be NOR0, NOR1, DRAM\r
	27	#define ARM_VE_REMAP_BASE 0x00000000\r
76bc1743	28	#define ARM_VE_REMAP_SZ SIZE_64MB\r
1d5d0ae9	29	\r
	30	// Motherboard Peripheral and On-chip peripheral\r
	31	#define ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE 0x10000000\r
76bc1743	32	#define ARM_VE_SMB_MB_ON_CHIP_PERIPH_SZ SIZE_256MB\r
1d5d0ae9	33	#define ARM_VE_BOARD_PERIPH_BASE 0x10000000\r
	34	#define ARM_VE_CHIP_PERIPH_BASE 0x10020000\r
	35	\r
	36	// SMC\r
	37	#define ARM_VE_SMC_BASE 0x40000000\r
	38	#define ARM_VE_SMC_SZ 0x1C000000\r
	39	\r
	40	// NOR Flash 1\r
	41	#define ARM_VE_SMB_NOR0_BASE 0x40000000\r
76bc1743	42	#define ARM_VE_SMB_NOR0_SZ SIZE_64MB\r
1d5d0ae9	43	// NOR Flash 2\r
1d5d0ae9	44	#define ARM_VE_SMB_NOR1_BASE 0x44000000\r
76bc1743	45	#define ARM_VE_SMB_NOR1_SZ SIZE_64MB\r
1d5d0ae9	46	// SRAM\r
1d5d0ae9	47	#define ARM_VE_SMB_SRAM_BASE 0x48000000\r
76bc1743	48	#define ARM_VE_SMB_SRAM_SZ SIZE_32MB\r
1d5d0ae9	49	// USB, Ethernet, VRAM\r
1d5d0ae9	50	#define ARM_VE_SMB_PERIPH_BASE 0x4C000000\r
76bc1743	51	#define PL111_CLCD_VRAM_MOTHERBOARD_BASE ARM_VE_SMB_PERIPH_BASE\r
76bc1743	52	#define ARM_VE_SMB_PERIPH_SZ SIZE_64MB\r
1d5d0ae9	53	\r
	54	// DRAM\r
	55	#define ARM_VE_DRAM_BASE 0x60000000\r
	56	#define ARM_VE_DRAM_SZ 0x40000000\r
7d0f2f23	57	// Inside the DRAM we allocate a section for the VRAM (Video RAM)\r
7d0f2f23	58	#define LCD_VRAM_CORE_TILE_BASE 0x64000000\r
1d5d0ae9	59	\r
	60	// External AXI between daughterboards (Logic Tile)\r
	61	#define ARM_VE_EXT_AXI_BASE 0xE0000000\r
76bc1743	62	#define ARM_VE_EXT_AXI_SZ 0x20000000 /* 512 MB */\r
	63	\r
	64	\r
	65	/***********************************************************************************\r
	66	Core Tile memory-mapped Peripherals\r
	67	************************************************************************************/\r
	68	\r
	69	// PL111 Colour LCD Controller - core tile\r
	70	#define PL111_CLCD_CORE_TILE_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x20000)\r
	71	\r
	72	// PL341 Dynamic Memory Controller Base\r
	73	#define ARM_VE_DMC_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE0000)\r
	74	\r
	75	// PL354 Static Memory Controller Base\r
	76	#define ARM_VE_SMC_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE1000)\r
1d5d0ae9	77	\r
1d5d0ae9	78	// System Configuration Controller register Base addresses\r
76bc1743	79	//#define ARM_VE_SYS_CFG_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE2000)\r
	80	#define ARM_VE_SYS_CFGRW0_REG (ARM_VE_BOARD_PERIPH_BASE + 0xE2000)\r
	81	#define ARM_VE_SYS_CFGRW1_REG (ARM_VE_BOARD_PERIPH_BASE + 0xE2004)\r
	82	#define ARM_VE_SYS_CFGRW2_REG (ARM_VE_BOARD_PERIPH_BASE + 0xE2008)\r
	83	\r
	84	#define ARM_PLATFORM_SCC_BASE ARM_VE_SYS_CFGRW0_REG\r
	85	\r
	86	// SP805 Watchdog on Cortex A9 core tile\r
	87	#define SP805_WDOG_CORE_TILE_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE5000)\r
	88	\r
	89	// BP147 TZPC Base Address\r
	90	#define ARM_VE_TZPC_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE6000)\r
	91	\r
	92	// PL301 Fast AXI Base Address\r
	93	#define ARM_VE_FAXI_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE9000)\r
	94	\r
	95	// TZASC Trust Zone Address Space Controller Base Address\r
	96	#define ARM_VE_TZASC_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xEC000)\r
	97	\r
	98	// PL310 L2x0 Cache Controller Base Address\r
	99	//#define ARM_VE_L2x0_CTLR_BASE 0x1E00A000\r
	100	\r
7d0f2f23	101	/***********************************************************************************\r
	102	Select between Motherboard and Core Tile peripherals\r
	103	************************************************************************************/\r
	104	\r
	105	// Specify which PL111 to use\r
	106	//#define PL111_CLCD_BASE PL111_CLCD_MOTHERBOARD_BASE\r
	107	#define PL111_CLCD_BASE PL111_CLCD_CORE_TILE_BASE\r
	108	\r
76bc1743	109	/***********************************************************************************\r
	110	Peripherals' misc settings\r
	111	************************************************************************************/\r
1d5d0ae9	112	\r
	113	#define ARM_VE_CFGRW1_TZASC_EN_BIT_MASK 0x2000\r
	114	#define ARM_VE_CFGRW1_REMAP_NOR0 0\r
	115	#define ARM_VE_CFGRW1_REMAP_NOR1 (1 << 28)\r
	116	#define ARM_VE_CFGRW1_REMAP_EXT_AXI (1 << 29)\r
	117	#define ARM_VE_CFGRW1_REMAP_DRAM (1 << 30)\r
	118	\r
76bc1743	119	// TZASC - Other settings\r
1d5d0ae9	120	#define ARM_VE_DECPROT_BIT_TZPC (1 << 6)\r
	121	#define ARM_VE_DECPROT_BIT_DMC_TZASC (1 << 11)\r
	122	#define ARM_VE_DECPROT_BIT_NMC_TZASC (1 << 12)\r
	123	#define ARM_VE_DECPROT_BIT_SMC_TZASC (1 << 13)\r
	124	#define ARM_VE_DECPROT_BIT_EXT_MAST_TZ (1)\r
	125	#define ARM_VE_DECPROT_BIT_DMC_TZASC_LOCK (1 << 3)\r
	126	#define ARM_VE_DECPROT_BIT_NMC_TZASC_LOCK (1 << 4)\r
	127	#define ARM_VE_DECPROT_BIT_SMC_TZASC_LOCK (1 << 5)\r
	128	\r
1d5d0ae9	129	\r
7d0f2f23	130	// PL111 Lcd\r
	131	#define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID 1\r
	132	\r
76bc1743	133	/***********************************************************************************\r
1d5d0ae9	134	// Interrupt Map\r
76bc1743	135	************************************************************************************/\r
1d5d0ae9	136	\r
1d5d0ae9	137	// Timer Interrupts\r
76bc1743	138	#define TIMER01_INTERRUPT_NUM 34\r
76bc1743	139	#define TIMER23_INTERRUPT_NUM 35\r
1d5d0ae9	140	\r
1d5d0ae9	141	\r
76bc1743	142	/***********************************************************************************\r
1d5d0ae9	143	// EFI Memory Map in Permanent Memory (DRAM)\r
76bc1743	144	************************************************************************************/\r
1d5d0ae9	145	\r
	146	// This region is allocated at the bottom of the DRAM. It will be used\r
	147	// for fixed address allocations such as Vector Table\r
	148	#define ARM_VE_EFI_FIX_ADDRESS_REGION_SZ SIZE_8MB\r
	149	\r
	150	// This region is the memory declared to PEI as permanent memory for PEI\r
	151	// and DXE. EFI stacks and heaps will be declared in this region.\r
76bc1743	152	#define ARM_VE_EFI_MEMORY_REGION_SZ SIZE_256MB\r
1d5d0ae9	153	\r
76bc1743	154	#endif\r