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ArmPkg/ArmPkg.dec: Redefined PcdSystemMemory(Base|Size) as UINT64
[mirror_edk2.git] / ArmPlatformPkg / ArmVExpressPkg / Library / ArmVExpressLibCTA15-A7 / CTA15-A7Mem.c
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295c2eb8 1/** @file\r
2*\r
3* Copyright (c) 2012, ARM Limited. All rights reserved.\r
4* \r
5* This program and the accompanying materials \r
6* are licensed and made available under the terms and conditions of the BSD License \r
7* which accompanies this distribution. The full text of the license may be found at \r
8* http://opensource.org/licenses/bsd-license.php \r
9*\r
10* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
11* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
12*\r
13**/\r
14\r
15#include <Library/ArmPlatformLib.h>\r
16#include <Library/DebugLib.h>\r
17#include <Library/HobLib.h>\r
18#include <Library/IoLib.h>\r
19#include <Library/MemoryAllocationLib.h>\r
20#include <Library/PcdLib.h>\r
21\r
22#include <ArmPlatform.h>\r
23\r
24#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 14\r
25\r
26// DDR attributes\r
27#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r
28#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED\r
29\r
30/**\r
31 Return the Virtual Memory Map of your platform\r
32\r
33 This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.\r
34\r
35 @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-\r
36 Virtual Memory mapping. This array must be ended by a zero-filled\r
37 entry\r
38\r
39**/\r
40VOID\r
41ArmPlatformGetVirtualMemoryMap (\r
42 IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap\r
43 )\r
44{\r
45 ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;\r
46 UINTN Index = 0;\r
47 ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;\r
48\r
49 ASSERT (VirtualMemoryMap != NULL);\r
50\r
51 VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));\r
52 if (VirtualMemoryTable == NULL) {\r
53 return;\r
54 }\r
55\r
56 if (FeaturePcdGet(PcdCacheEnable) == TRUE) {\r
57 CacheAttributes = DDR_ATTRIBUTES_CACHED;\r
58 } else {\r
59 CacheAttributes = DDR_ATTRIBUTES_UNCACHED;\r
60 }\r
61\r
295c2eb8 62#ifdef ARM_BIGLITTLE_TC2\r
63 // Secure NOR0 Flash\r
64 VirtualMemoryTable[Index].PhysicalBase = ARM_VE_SEC_NOR0_BASE;\r
65 VirtualMemoryTable[Index].VirtualBase = ARM_VE_SEC_NOR0_BASE;\r
66 VirtualMemoryTable[Index].Length = ARM_VE_SEC_NOR0_SZ;\r
67 VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
68 // Secure RAM\r
69 VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SEC_RAM0_BASE;\r
70 VirtualMemoryTable[Index].VirtualBase = ARM_VE_SEC_RAM0_BASE;\r
71 VirtualMemoryTable[Index].Length = ARM_VE_SEC_RAM0_SZ;\r
72 VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
73#endif\r
74\r
75 // SMB CS0 - NOR0 Flash\r
76 VirtualMemoryTable[Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE;\r
77 VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE;\r
78 VirtualMemoryTable[Index].Length = SIZE_256KB * 255;\r
79 VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
80 // Environment Variables region\r
81 VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE + (SIZE_256KB * 255);\r
82 VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE + (SIZE_256KB * 255);\r
83 VirtualMemoryTable[Index].Length = SIZE_64KB * 4;\r
84 VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
85\r
86 // SMB CS1 or CS4 - NOR1 Flash\r
87 VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR1_BASE;\r
88 VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR1_BASE;\r
89 VirtualMemoryTable[Index].Length = SIZE_256KB * 255;\r
90 VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
91 // Environment Variables region\r
92 VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR1_BASE + (SIZE_256KB * 255);\r
93 VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR1_BASE + (SIZE_256KB * 255);\r
94 VirtualMemoryTable[Index].Length = SIZE_64KB * 4;\r
95 VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
96\r
97 // SMB CS3 or CS1 - PSRAM\r
98 VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE;\r
99 VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_SRAM_BASE;\r
100 VirtualMemoryTable[Index].Length = ARM_VE_SMB_SRAM_SZ;\r
101 VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
102\r
103 // Motherboard peripherals\r
104 VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;\r
105 VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE;\r
106 VirtualMemoryTable[Index].Length = ARM_VE_SMB_PERIPH_SZ;\r
107 VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
108\r
109#ifdef ARM_BIGLITTLE_TC2\r
110 // Non-secure ROM\r
111 VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_TC2_NON_SECURE_ROM_BASE;\r
112 VirtualMemoryTable[Index].VirtualBase = ARM_VE_TC2_NON_SECURE_ROM_BASE;\r
113 VirtualMemoryTable[Index].Length = ARM_VE_TC2_NON_SECURE_ROM_SZ;\r
114 VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
115#endif\r
116\r
117 // OnChip peripherals\r
118 VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_ONCHIP_PERIPH_BASE;\r
119 VirtualMemoryTable[Index].VirtualBase = ARM_VE_ONCHIP_PERIPH_BASE;\r
120 VirtualMemoryTable[Index].Length = ARM_VE_ONCHIP_PERIPH_SZ;\r
121 VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
122\r
123 // SCC Region\r
124 VirtualMemoryTable[++Index].PhysicalBase = ARM_CTA15A7_SCC_BASE;\r
125 VirtualMemoryTable[Index].VirtualBase = ARM_CTA15A7_SCC_BASE;\r
126 VirtualMemoryTable[Index].Length = SIZE_64KB;\r
127 VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
128\r
129#ifdef ARM_BIGLITTLE_TC2\r
130 // TC2 OnChip non-secure SRAM\r
131 VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_TC2_NON_SECURE_SRAM_BASE;\r
132 VirtualMemoryTable[Index].VirtualBase = ARM_VE_TC2_NON_SECURE_SRAM_BASE;\r
133 VirtualMemoryTable[Index].Length = ARM_VE_TC2_NON_SECURE_SRAM_SZ;\r
134 VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
135#endif\r
136\r
137#ifndef ARM_BIGLITTLE_TC2\r
138 // Workaround for SRAM bug in RTSM\r
c357fd6a 139 if (PcdGet64 (PcdSystemMemoryBase) != 0x80000000) {\r
295c2eb8 140 VirtualMemoryTable[++Index].PhysicalBase = 0x80000000;\r
141 VirtualMemoryTable[Index].VirtualBase = 0x80000000;\r
c357fd6a 142 VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemoryBase) - 0x80000000;\r
295c2eb8 143 VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
144 }\r
145#endif\r
146\r
147 // DDR\r
c357fd6a
OM		 148 VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);\r
149 VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase);\r
150 VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize);\r
295c2eb8 151 VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
152\r
e8ee4b2d
OM		 153 // Detect if it is a 1GB or 2GB Test Chip\r
154 // [16:19]: 0=1GB TC2, 1=2GB TC2\r
155 if (MmioRead32(ARM_VE_SYS_PROCID0_REG) & (0xF << 16)) {\r
156 DEBUG((EFI_D_ERROR,"Info: 2GB Test Chip 2 detected.\n"));\r
157 BuildResourceDescriptorHob (\r
158 EFI_RESOURCE_SYSTEM_MEMORY,\r
159 EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
160 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
161 EFI_RESOURCE_ATTRIBUTE_TESTED,\r
c357fd6a 162 PcdGet64 (PcdSystemMemoryBase) + PcdGet64 (PcdSystemMemorySize),\r
e8ee4b2d
OM		 163 SIZE_1GB\r
164 );\r
165\r
166 // Map the additional 1GB into the MMU\r
c357fd6a
OM		 167 VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase) + PcdGet64 (PcdSystemMemorySize);\r
168 VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase) + PcdGet64 (PcdSystemMemorySize);\r
e8ee4b2d
OM		 169 VirtualMemoryTable[Index].Length = SIZE_1GB;\r
170 VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
171 }\r
172\r
295c2eb8 173 // End of Table\r
174 VirtualMemoryTable[++Index].PhysicalBase = 0;\r
175 VirtualMemoryTable[Index].VirtualBase = 0;\r
176 VirtualMemoryTable[Index].Length = 0;\r
177 VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
178\r
179 ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);\r
180\r
181 *VirtualMemoryMap = VirtualMemoryTable;\r
182}\r
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