ArmPlatformPkg: Minor code changes (comments, misspellings, coding stylei, line endings)
[mirror_edk2.git] / ArmPlatformPkg / ArmVExpressPkg / Library / ArmVExpressLibCTA9x4 / CTA9x4.c
CommitLineData
1d5d0ae9 1/** @file
2*
0db25ccc 3* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
1d5d0ae9 4*
5* This program and the accompanying materials
6* are licensed and made available under the terms and conditions of the BSD License
7* which accompanies this distribution. The full text of the license may be found at
8* http://opensource.org/licenses/bsd-license.php
9*
10* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12*
13**/
14
15#include <Library/IoLib.h>
1d5d0ae9 16#include <Library/ArmPlatformLib.h>
17#include <Library/DebugLib.h>
18#include <Library/PcdLib.h>
23792dea 19#include <Library/SerialPortLib.h>
20
1d5d0ae9 21#include <Drivers/PL341Dmc.h>
8e06b586 22#include <Drivers/PL301Axi.h>
23792dea 23#include <Drivers/SP804Timer.h>
2637d1ef 24
44788bae 25#include <Ppi/ArmMpCoreInfo.h>
26
5cc45b70 27#include <ArmPlatform.h>
28
e862cd50 29#define SerialPrint(txt) SerialPortWrite ((UINT8*)(txt), AsciiStrLen(txt)+1);
1d5d0ae9 30
44788bae 31ARM_CORE_INFO mVersatileExpressMpCoreInfoCTA9x4[] = {
32 {
33 // Cluster 0, Core 0
34 0x0, 0x0,
35
36 // MP Core MailBox Set/Get/Clear Addresses and Clear Value
37 (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
38 (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
39 (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
40 (UINT64)0xFFFFFFFF
41 },
42 {
43 // Cluster 0, Core 1
44 0x0, 0x1,
45
46 // MP Core MailBox Set/Get/Clear Addresses and Clear Value
47 (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
48 (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
49 (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
50 (UINT64)0xFFFFFFFF
51 },
52 {
53 // Cluster 0, Core 2
54 0x0, 0x2,
55
56 // MP Core MailBox Set/Get/Clear Addresses and Clear Value
57 (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
58 (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
59 (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
60 (UINT64)0xFFFFFFFF
61 },
62 {
63 // Cluster 0, Core 3
64 0x0, 0x3,
65
66 // MP Core MailBox Set/Get/Clear Addresses and Clear Value
67 (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
68 (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
69 (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
70 (UINT64)0xFFFFFFFF
71 }
72};
73
1d5d0ae9 74// DDR2 timings
8be5d4d6 75PL341_DMC_CONFIG DDRTimings = {
8be5d4d6 76 .MaxChip = 1,
77 .IsUserCfg = TRUE,
78 .User0Cfg = 0x7C924924,
79 .User2Cfg = (TC_UIOLHXC_VALUE << TC_UIOLHNC_SHIFT) | (TC_UIOLHXC_VALUE << TC_UIOLHPC_SHIFT) | (0x1 << TC_UIOHOCT_SHIFT) | (0x1 << TC_UIOHSTOP_SHIFT),
80 .HasQos = TRUE,
06a89733 81 .RefreshPeriod = 0x3D0,
82 .CasLatency = 0x8,
83 .WriteLatency = 0x3,
8be5d4d6 84 .t_mrd = 0x2,
85 .t_ras = 0xA,
86 .t_rc = 0xE,
87 .t_rcd = 0x104,
88 .t_rfc = 0x2f32,
89 .t_rp = 0x14,
90 .t_rrd = 0x2,
91 .t_wr = 0x4,
92 .t_wtr = 0x2,
93 .t_xp = 0x2,
94 .t_xsr = 0xC8,
95 .t_esr = 0x14,
96 .MemoryCfg = DMC_MEMORY_CONFIG_ACTIVE_CHIP_1 | DMC_MEMORY_CONFIG_BURST_4 |
97 DMC_MEMORY_CONFIG_ROW_ADDRESS_15 | DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10,
98 .MemoryCfg2 = DMC_MEMORY_CFG2_DQM_INIT | DMC_MEMORY_CFG2_CKE_INIT |
99 DMC_MEMORY_CFG2_BANK_BITS_3 | DMC_MEMORY_CFG2_MEM_WIDTH_32,
100 .MemoryCfg3 = 0x00000001,
101 .ChipCfg0 = 0x00010000,
102 .t_faw = 0x00000A0D,
103 .ModeReg = DDR2_MR_BURST_LENGTH_4 | DDR2_MR_CAS_LATENCY_4 | DDR2_MR_WR_CYCLES_4,
104 .ExtModeReg = DDR_EMR_RTT_50R | (DDR_EMR_ODS_VAL << DDR_EMR_ODS_MASK),
1d5d0ae9 105};
106
a534d714 107/**
108 Return the current Boot Mode
109
110 This function returns the boot reason on the platform
111
112 @return Return the current Boot Mode of the platform
113
114**/
115EFI_BOOT_MODE
116ArmPlatformGetBootMode (
117 VOID
118 )
119{
12c5ae23 120 if (MmioRead32(ARM_VE_SYS_FLAGS_NV_REG) == 0) {
121 return BOOT_WITH_FULL_CONFIGURATION;
122 } else {
123 return BOOT_ON_S2_RESUME;
124 }
a534d714 125}
126
aa01abaa 127/**
128 Initialize controllers that must setup in the normal world
129
5cc45b70 130 This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
aa01abaa 131 in the PEI phase.
132
133**/
134VOID
135ArmPlatformNormalInitialize (
136 VOID
137 )
138{
23792dea 139 // Configure periodic timer (TIMER0) for 1MHz operation
140 MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);
141 // Configure 1MHz clock
142 MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK);
143 // configure SP810 to use 1MHz clock and disable
144 MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);
145 // Configure SP810 to use 1MHz clock and disable
146 MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);
aa01abaa 147}
148
1d5d0ae9 149/**
150 Initialize the system (or sometimes called permanent) memory
151
152 This memory is generally represented by the DRAM.
153
154**/
aa01abaa 155VOID
156ArmPlatformInitializeSystemMemory (
157 VOID
158 )
159{
8d0fe26c 160 UINT32 Value;
161
162 // Memory Map remapping
163 if (FeaturePcdGet(PcdNorFlashRemapping)) {
164 SerialPrint ("Secure ROM at 0x0\n\r");
165 } else {
166 Value = MmioRead32(ARM_VE_SYS_CFGRW1_REG); //Scc - CFGRW1
167 // Remap the DRAM to 0x0
168 MmioWrite32(ARM_VE_SYS_CFGRW1_REG, (Value & 0x0FFFFFFF) | ARM_VE_CFGRW1_REMAP_DRAM);
169 }
170
06a89733 171 PL341DmcInit(ARM_VE_DMC_BASE, &DDRTimings);
aa01abaa 172 PL301AxiInit(ARM_VE_FAXI_BASE);
1d5d0ae9 173}
44788bae 174
175EFI_STATUS
176PrePeiCoreGetMpCoreInfo (
177 OUT UINTN *CoreCount,
178 OUT ARM_CORE_INFO **ArmCoreTable
179 )
180{
181 *CoreCount = sizeof(mVersatileExpressMpCoreInfoCTA9x4) / sizeof(ARM_CORE_INFO);
182 *ArmCoreTable = mVersatileExpressMpCoreInfoCTA9x4;
183
184 return EFI_SUCCESS;
185}
186
187// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore
188EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;
189ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
190
191EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
192 {
193 EFI_PEI_PPI_DESCRIPTOR_PPI,
194 &mArmMpCoreInfoPpiGuid,
195 &mMpCoreInfoPpi
196 }
197};
198
77de7e53 199VOID
200ArmPlatformGetPlatformPpiList (
201 OUT UINTN *PpiListSize,
202 OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
203 )
204{
44788bae 205 *PpiListSize = sizeof(gPlatformPpiTable);
206 *PpiList = gPlatformPpiTable;
77de7e53 207}
208