ARM Packages: Removed trailing spaces

[mirror_edk2.git] / ArmPlatformPkg / ArmVExpressPkg / Library / ArmVExpressLibCTA9x4 / CTA9x4.c

/** @file\r
*\r
*  Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
*\r
*  This program and the accompanying materials\r
*  are licensed and made available under the terms and conditions of the BSD License\r
*  which accompanies this distribution.  The full text of the license may be found at\r
*  http://opensource.org/licenses/bsd-license.php\r
*\r
*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
*\r
**/\r
\r
#include <Library/IoLib.h>\r
#include <Library/ArmPlatformLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/PcdLib.h>\r
\r
#include <Drivers/PL341Dmc.h>\r
#include <Drivers/PL301Axi.h>\r
#include <Drivers/SP804Timer.h>\r
\r
#include <Ppi/ArmMpCoreInfo.h>\r
\r
#include <ArmPlatform.h>\r
\r
ARM_CORE_INFO mVersatileExpressMpCoreInfoCTA9x4[] = {\r
  {\r
    // Cluster 0, Core 0\r
    0x0, 0x0,\r
\r
    // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
    (UINT64)0xFFFFFFFF\r
  },\r
  {\r
    // Cluster 0, Core 1\r
    0x0, 0x1,\r
\r
    // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
    (UINT64)0xFFFFFFFF\r
  },\r
  {\r
    // Cluster 0, Core 2\r
    0x0, 0x2,\r
\r
    // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
    (UINT64)0xFFFFFFFF\r
  },\r
  {\r
    // Cluster 0, Core 3\r
    0x0, 0x3,\r
\r
    // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
    (UINT64)0xFFFFFFFF\r
  }\r
};\r
\r
// DDR2 timings\r
PL341_DMC_CONFIG DDRTimings = {\r
  .MaxChip   = 1,\r
  .IsUserCfg = TRUE,\r
  .User0Cfg = 0x7C924924,\r
  .User2Cfg = (TC_UIOLHXC_VALUE << TC_UIOLHNC_SHIFT) | (TC_UIOLHXC_VALUE << TC_UIOLHPC_SHIFT) | (0x1 << TC_UIOHOCT_SHIFT) | (0x1 << TC_UIOHSTOP_SHIFT),\r
  .HasQos    = TRUE,\r
  .RefreshPeriod  = 0x3D0,\r
  .CasLatency  = 0x8,\r
  .WriteLatency  = 0x3,\r
  .t_mrd    = 0x2,\r
  .t_ras    = 0xA,\r
  .t_rc   = 0xE,\r
  .t_rcd    = 0x104,\r
  .t_rfc    = 0x2f32,\r
  .t_rp   = 0x14,\r
  .t_rrd    = 0x2,\r
  .t_wr   = 0x4,\r
  .t_wtr    = 0x2,\r
  .t_xp   = 0x2,\r
  .t_xsr    = 0xC8,\r
  .t_esr    = 0x14,\r
  .MemoryCfg   = DMC_MEMORY_CONFIG_ACTIVE_CHIP_1 | DMC_MEMORY_CONFIG_BURST_4 |\r
                        DMC_MEMORY_CONFIG_ROW_ADDRESS_15 | DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10,\r
  .MemoryCfg2  = DMC_MEMORY_CFG2_DQM_INIT | DMC_MEMORY_CFG2_CKE_INIT |\r
            DMC_MEMORY_CFG2_BANK_BITS_3 | DMC_MEMORY_CFG2_MEM_WIDTH_32,\r
  .MemoryCfg3  = 0x00000001,\r
  .ChipCfg0    = 0x00010000,\r
  .t_faw    = 0x00000A0D,\r
  .ModeReg = DDR2_MR_BURST_LENGTH_4 | DDR2_MR_CAS_LATENCY_4 | DDR2_MR_WR_CYCLES_4,\r
  .ExtModeReg = DDR_EMR_RTT_50R | (DDR_EMR_ODS_VAL << DDR_EMR_ODS_MASK),\r
};\r
\r
/**\r
  Return the current Boot Mode\r
\r
  This function returns the boot reason on the platform\r
\r
  @return   Return the current Boot Mode of the platform\r
\r
**/\r
EFI_BOOT_MODE\r
ArmPlatformGetBootMode (\r
  VOID\r
  )\r
{\r
  if (MmioRead32(ARM_VE_SYS_FLAGS_NV_REG) == 0) {\r
    return BOOT_WITH_FULL_CONFIGURATION;\r
  } else {\r
    return BOOT_ON_S2_RESUME;\r
  }\r
}\r
\r
/**\r
  Initialize controllers that must setup in the normal world\r
\r
  This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei\r
  in the PEI phase.\r
\r
**/\r
RETURN_STATUS\r
ArmPlatformInitialize (\r
  IN  UINTN                     MpId\r
  )\r
{\r
  if (!ArmPlatformIsPrimaryCore (MpId)) {\r
    return RETURN_SUCCESS;\r
  }\r
\r
  // Configure periodic timer (TIMER0) for 1MHz operation\r
  MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);\r
  // Configure 1MHz clock\r
  MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK);\r
  // configure SP810 to use 1MHz clock and disable\r
  MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);\r
  // Configure SP810 to use 1MHz clock and disable\r
  MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);\r
\r
  return RETURN_SUCCESS;\r
}\r
\r
/**\r
  Initialize the system (or sometimes called permanent) memory\r
\r
  This memory is generally represented by the DRAM.\r
\r
**/\r
VOID\r
ArmPlatformInitializeSystemMemory (\r
  VOID\r
  )\r
{\r
  PL341DmcInit (ARM_VE_DMC_BASE, &DDRTimings);\r
  PL301AxiInit (ARM_VE_FAXI_BASE);\r
}\r
\r
EFI_STATUS\r
PrePeiCoreGetMpCoreInfo (\r
  OUT UINTN                   *CoreCount,\r
  OUT ARM_CORE_INFO           **ArmCoreTable\r
  )\r
{\r
  *CoreCount    = sizeof(mVersatileExpressMpCoreInfoCTA9x4) / sizeof(ARM_CORE_INFO);\r
  *ArmCoreTable = mVersatileExpressMpCoreInfoCTA9x4;\r
\r
  return EFI_SUCCESS;\r
}\r
\r
// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore\r
EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;\r
ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };\r
\r
EFI_PEI_PPI_DESCRIPTOR      gPlatformPpiTable[] = {\r
  {\r
    EFI_PEI_PPI_DESCRIPTOR_PPI,\r
    &mArmMpCoreInfoPpiGuid,\r
    &mMpCoreInfoPpi\r
  }\r
};\r
\r
VOID\r
ArmPlatformGetPlatformPpiList (\r
  OUT UINTN                   *PpiListSize,\r
  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList\r
  )\r
{\r
  *PpiListSize = sizeof(gPlatformPpiTable);\r
  *PpiList = gPlatformPpiTable;\r
}\r
\r