[mirror_edk2.git] / ArmPlatformPkg / ArmVExpressPkg / Library / ArmVExpressLibCTA9x4 / CTA9x4.c

/** @file\r
*\r
*  Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
*  \r
*  This program and the accompanying materials                          \r
*  are licensed and made available under the terms and conditions of the BSD License         \r
*  which accompanies this distribution.  The full text of the license may be found at        \r
*  http://opensource.org/licenses/bsd-license.php                                            \r
*\r
*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
*\r
**/\r
\r
#include <Library/IoLib.h>\r
#include <Library/ArmPlatformLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/SerialPortLib.h>\r
\r
#include <Drivers/PL341Dmc.h>\r
#include <Drivers/PL301Axi.h>\r
#include <Drivers/SP804Timer.h>\r
\r
#include <Ppi/ArmMpCoreInfo.h>\r
\r
#include <ArmPlatform.h>\r
\r
#define SerialPrint(txt)  SerialPortWrite ((UINT8*)(txt), AsciiStrLen(txt)+1);\r
\r
ARM_CORE_INFO mVersatileExpressMpCoreInfoCTA9x4[] = {\r
  {\r
    // Cluster 0, Core 0\r
    0x0, 0x0,\r
\r
    // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
    (UINT64)0xFFFFFFFF\r
  },\r
  {\r
    // Cluster 0, Core 1\r
    0x0, 0x1,\r
\r
    // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
    (UINT64)0xFFFFFFFF\r
  },\r
  {\r
    // Cluster 0, Core 2\r
    0x0, 0x2,\r
\r
    // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
    (UINT64)0xFFFFFFFF\r
  },\r
  {\r
    // Cluster 0, Core 3\r
    0x0, 0x3,\r
\r
    // MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
    (UINT64)0xFFFFFFFF\r
  }\r
};\r
\r
// DDR2 timings\r
PL341_DMC_CONFIG DDRTimings = {\r
  .MaxChip   = 1,\r
  .IsUserCfg = TRUE,\r
  .User0Cfg = 0x7C924924,\r
  .User2Cfg = (TC_UIOLHXC_VALUE << TC_UIOLHNC_SHIFT) | (TC_UIOLHXC_VALUE << TC_UIOLHPC_SHIFT) | (0x1 << TC_UIOHOCT_SHIFT) | (0x1 << TC_UIOHSTOP_SHIFT),\r
  .HasQos    = TRUE,\r
  .RefreshPeriod  = 0x3D0,\r
  .CasLatency  = 0x8,\r
  .WriteLatency  = 0x3,\r
  .t_mrd    = 0x2,\r
  .t_ras    = 0xA,\r
  .t_rc   = 0xE,\r
  .t_rcd    = 0x104,\r
  .t_rfc    = 0x2f32,\r
  .t_rp   = 0x14,\r
  .t_rrd    = 0x2,\r
  .t_wr   = 0x4,\r
  .t_wtr    = 0x2,\r
  .t_xp   = 0x2,\r
  .t_xsr    = 0xC8,\r
  .t_esr    = 0x14,\r
  .MemoryCfg   = DMC_MEMORY_CONFIG_ACTIVE_CHIP_1 | DMC_MEMORY_CONFIG_BURST_4 |\r
                        DMC_MEMORY_CONFIG_ROW_ADDRESS_15 | DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10,\r
  .MemoryCfg2  = DMC_MEMORY_CFG2_DQM_INIT | DMC_MEMORY_CFG2_CKE_INIT |\r
            DMC_MEMORY_CFG2_BANK_BITS_3 | DMC_MEMORY_CFG2_MEM_WIDTH_32,\r
  .MemoryCfg3  = 0x00000001,\r
  .ChipCfg0    = 0x00010000,\r
  .t_faw    = 0x00000A0D,\r
  .ModeReg = DDR2_MR_BURST_LENGTH_4 | DDR2_MR_CAS_LATENCY_4 | DDR2_MR_WR_CYCLES_4,\r
  .ExtModeReg = DDR_EMR_RTT_50R | (DDR_EMR_ODS_VAL << DDR_EMR_ODS_MASK),\r
};\r
\r
/**\r
  Return the current Boot Mode\r
\r
  This function returns the boot reason on the platform\r
\r
  @return   Return the current Boot Mode of the platform\r
\r
**/\r
EFI_BOOT_MODE\r
ArmPlatformGetBootMode (\r
  VOID\r
  )\r
{\r
  if (MmioRead32(ARM_VE_SYS_FLAGS_NV_REG) == 0) {\r
    return BOOT_WITH_FULL_CONFIGURATION;\r
  } else {\r
    return BOOT_ON_S2_RESUME;\r
  }\r
}\r
\r
/**\r
  Initialize controllers that must setup in the normal world\r
\r
  This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei\r
  in the PEI phase.\r
\r
**/\r
RETURN_STATUS\r
ArmPlatformInitialize (\r
  IN  UINTN                     MpId\r
  )\r
{\r
  if (!ArmPlatformIsPrimaryCore (MpId)) {\r
    return RETURN_SUCCESS;\r
  }\r
\r
  // Configure periodic timer (TIMER0) for 1MHz operation\r
  MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);\r
  // Configure 1MHz clock\r
  MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK);\r
  // configure SP810 to use 1MHz clock and disable\r
  MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);\r
  // Configure SP810 to use 1MHz clock and disable\r
  MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);\r
\r
  return RETURN_SUCCESS;\r
}\r
\r
/**\r
  Initialize the system (or sometimes called permanent) memory\r
\r
  This memory is generally represented by the DRAM.\r
\r
**/\r
VOID\r
ArmPlatformInitializeSystemMemory (\r
  VOID\r
  )\r
{\r
  UINT32 Value;\r
\r
  // Memory Map remapping\r
  if (FeaturePcdGet(PcdNorFlashRemapping)) {\r
    SerialPrint ("Secure ROM at 0x0\n\r");\r
  } else {\r
    Value = MmioRead32(ARM_VE_SYS_CFGRW1_REG); //Scc - CFGRW1\r
    // Remap the DRAM to 0x0\r
    MmioWrite32(ARM_VE_SYS_CFGRW1_REG, (Value & 0x0FFFFFFF) | ARM_VE_CFGRW1_REMAP_DRAM);\r
  }\r
\r
  PL341DmcInit(ARM_VE_DMC_BASE, &DDRTimings);\r
  PL301AxiInit(ARM_VE_FAXI_BASE);\r
}\r
\r
EFI_STATUS\r
PrePeiCoreGetMpCoreInfo (\r
  OUT UINTN                   *CoreCount,\r
  OUT ARM_CORE_INFO           **ArmCoreTable\r
  )\r
{\r
  *CoreCount    = sizeof(mVersatileExpressMpCoreInfoCTA9x4) / sizeof(ARM_CORE_INFO);\r
  *ArmCoreTable = mVersatileExpressMpCoreInfoCTA9x4;\r
\r
  return EFI_SUCCESS;\r
}\r
\r
// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore\r
EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;\r
ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };\r
\r
EFI_PEI_PPI_DESCRIPTOR      gPlatformPpiTable[] = {\r
  {\r
    EFI_PEI_PPI_DESCRIPTOR_PPI,\r
    &mArmMpCoreInfoPpiGuid,\r
    &mMpCoreInfoPpi\r
  }\r
};\r
\r
VOID\r
ArmPlatformGetPlatformPpiList (\r
  OUT UINTN                   *PpiListSize,\r
  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList\r
  )\r
{\r
  *PpiListSize = sizeof(gPlatformPpiTable);\r
  *PpiList = gPlatformPpiTable;\r
}\r
\r
Commit	Line	Data
1e57a462	1	/** @file\r
	2	*\r
	3	* Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
	4	* \r
	5	* This program and the accompanying materials \r
	6	* are licensed and made available under the terms and conditions of the BSD License \r
	7	* which accompanies this distribution. The full text of the license may be found at \r
	8	* http://opensource.org/licenses/bsd-license.php \r
	9	*\r
	10	* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	11	* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
	12	*\r
	13	**/\r
	14	\r
	15	#include <Library/IoLib.h>\r
	16	#include <Library/ArmPlatformLib.h>\r
	17	#include <Library/DebugLib.h>\r
	18	#include <Library/PcdLib.h>\r
	19	#include <Library/SerialPortLib.h>\r
	20	\r
	21	#include <Drivers/PL341Dmc.h>\r
	22	#include <Drivers/PL301Axi.h>\r
	23	#include <Drivers/SP804Timer.h>\r
	24	\r
	25	#include <Ppi/ArmMpCoreInfo.h>\r
	26	\r
	27	#include <ArmPlatform.h>\r
	28	\r
	29	#define SerialPrint(txt) SerialPortWrite ((UINT8*)(txt), AsciiStrLen(txt)+1);\r
	30	\r
	31	ARM_CORE_INFO mVersatileExpressMpCoreInfoCTA9x4[] = {\r
	32	{\r
	33	// Cluster 0, Core 0\r
	34	0x0, 0x0,\r
	35	\r
	36	// MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
	37	(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
	38	(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
	39	(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
	40	(UINT64)0xFFFFFFFF\r
	41	},\r
	42	{\r
	43	// Cluster 0, Core 1\r
	44	0x0, 0x1,\r
	45	\r
	46	// MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
	47	(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
	48	(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
	49	(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
	50	(UINT64)0xFFFFFFFF\r
	51	},\r
	52	{\r
	53	// Cluster 0, Core 2\r
	54	0x0, 0x2,\r
	55	\r
	56	// MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
	57	(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
	58	(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
	59	(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
	60	(UINT64)0xFFFFFFFF\r
	61	},\r
	62	{\r
	63	// Cluster 0, Core 3\r
	64	0x0, 0x3,\r
65	\r
66	// MP Core MailBox Set/Get/Clear Addresses and Clear Value\r
67	(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,\r
68	(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,\r
69	(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,\r
70	(UINT64)0xFFFFFFFF\r
71	}\r
72	};\r
73	\r
74	// DDR2 timings\r
75	PL341_DMC_CONFIG DDRTimings = {\r
76	.MaxChip = 1,\r
77	.IsUserCfg = TRUE,\r
78	.User0Cfg = 0x7C924924,\r
79	.User2Cfg = (TC_UIOLHXC_VALUE << TC_UIOLHNC_SHIFT) \| (TC_UIOLHXC_VALUE << TC_UIOLHPC_SHIFT) \| (0x1 << TC_UIOHOCT_SHIFT) \| (0x1 << TC_UIOHSTOP_SHIFT),\r
80	.HasQos = TRUE,\r
81	.RefreshPeriod = 0x3D0,\r
82	.CasLatency = 0x8,\r
83	.WriteLatency = 0x3,\r
84	.t_mrd = 0x2,\r
85	.t_ras = 0xA,\r
86	.t_rc = 0xE,\r
87	.t_rcd = 0x104,\r
88	.t_rfc = 0x2f32,\r
89	.t_rp = 0x14,\r
90	.t_rrd = 0x2,\r
91	.t_wr = 0x4,\r
92	.t_wtr = 0x2,\r
93	.t_xp = 0x2,\r
94	.t_xsr = 0xC8,\r
95	.t_esr = 0x14,\r
96	.MemoryCfg = DMC_MEMORY_CONFIG_ACTIVE_CHIP_1 \| DMC_MEMORY_CONFIG_BURST_4 \|\r
97	DMC_MEMORY_CONFIG_ROW_ADDRESS_15 \| DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10,\r
98	.MemoryCfg2 = DMC_MEMORY_CFG2_DQM_INIT \| DMC_MEMORY_CFG2_CKE_INIT \|\r
99	DMC_MEMORY_CFG2_BANK_BITS_3 \| DMC_MEMORY_CFG2_MEM_WIDTH_32,\r
100	.MemoryCfg3 = 0x00000001,\r
101	.ChipCfg0 = 0x00010000,\r
102	.t_faw = 0x00000A0D,\r
103	.ModeReg = DDR2_MR_BURST_LENGTH_4 \| DDR2_MR_CAS_LATENCY_4 \| DDR2_MR_WR_CYCLES_4,\r
104	.ExtModeReg = DDR_EMR_RTT_50R \| (DDR_EMR_ODS_VAL << DDR_EMR_ODS_MASK),\r
105	};\r
106	\r
107	/**\r
108	Return the current Boot Mode\r
109	\r
110	This function returns the boot reason on the platform\r
111	\r
112	@return Return the current Boot Mode of the platform\r
113	\r
114	**/\r
115	EFI_BOOT_MODE\r
116	ArmPlatformGetBootMode (\r
117	VOID\r
118	)\r
119	{\r
120	if (MmioRead32(ARM_VE_SYS_FLAGS_NV_REG) == 0) {\r
121	return BOOT_WITH_FULL_CONFIGURATION;\r
122	} else {\r
123	return BOOT_ON_S2_RESUME;\r
124	}\r
125	}\r
126	\r
127	/**\r
128	Initialize controllers that must setup in the normal world\r
129	\r
130	This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei\r
131	in the PEI phase.\r
132	\r
133	**/\r
134	RETURN_STATUS\r
135	ArmPlatformInitialize (\r
136	IN UINTN MpId\r
137	)\r
138	{\r
bebda7ce	139	if (!ArmPlatformIsPrimaryCore (MpId)) {\r
1e57a462	140	return RETURN_SUCCESS;\r
	141	}\r
	142	\r
	143	// Configure periodic timer (TIMER0) for 1MHz operation\r
	144	MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);\r
	145	// Configure 1MHz clock\r
	146	MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK);\r
	147	// configure SP810 to use 1MHz clock and disable\r
	148	MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);\r
	149	// Configure SP810 to use 1MHz clock and disable\r
	150	MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);\r
	151	\r
	152	return RETURN_SUCCESS;\r
	153	}\r
	154	\r
	155	/**\r
	156	Initialize the system (or sometimes called permanent) memory\r
	157	\r
	158	This memory is generally represented by the DRAM.\r
	159	\r
	160	**/\r
	161	VOID\r
	162	ArmPlatformInitializeSystemMemory (\r
	163	VOID\r
	164	)\r
	165	{\r
	166	UINT32 Value;\r
	167	\r
	168	// Memory Map remapping\r
	169	if (FeaturePcdGet(PcdNorFlashRemapping)) {\r
	170	SerialPrint ("Secure ROM at 0x0\n\r");\r
	171	} else {\r
	172	Value = MmioRead32(ARM_VE_SYS_CFGRW1_REG); //Scc - CFGRW1\r
	173	// Remap the DRAM to 0x0\r
	174	MmioWrite32(ARM_VE_SYS_CFGRW1_REG, (Value & 0x0FFFFFFF) \| ARM_VE_CFGRW1_REMAP_DRAM);\r
	175	}\r
	176	\r
	177	PL341DmcInit(ARM_VE_DMC_BASE, &DDRTimings);\r
	178	PL301AxiInit(ARM_VE_FAXI_BASE);\r
	179	}\r
	180	\r
	181	EFI_STATUS\r
	182	PrePeiCoreGetMpCoreInfo (\r
	183	OUT UINTN *CoreCount,\r
	184	OUT ARM_CORE_INFO **ArmCoreTable\r
	185	)\r
	186	{\r
	187	*CoreCount = sizeof(mVersatileExpressMpCoreInfoCTA9x4) / sizeof(ARM_CORE_INFO);\r
	188	*ArmCoreTable = mVersatileExpressMpCoreInfoCTA9x4;\r
	189	\r
	190	return EFI_SUCCESS;\r
	191	}\r
	192	\r
	193	// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore\r
	194	EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;\r
	195	ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };\r
	196	\r
	197	EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {\r
	198	{\r
	199	EFI_PEI_PPI_DESCRIPTOR_PPI,\r
	200	&mArmMpCoreInfoPpiGuid,\r
	201	&mMpCoreInfoPpi\r
	202	}\r
	203	};\r
204	\r
205	VOID\r
206	ArmPlatformGetPlatformPpiList (\r
207	OUT UINTN *PpiListSize,\r
208	OUT EFI_PEI_PPI_DESCRIPTOR **PpiList\r
209	)\r
210	{\r
211	*PpiListSize = sizeof(gPlatformPpiTable);\r
212	*PpiList = gPlatformPpiTable;\r
213	}\r
214	\r