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1d5d0ae9 | 1 | /** @file |
2 | * | |
3 | * Copyright (c) 2011, ARM Limited. All rights reserved. | |
4 | * | |
5 | * This program and the accompanying materials | |
6 | * are licensed and made available under the terms and conditions of the BSD License | |
7 | * which accompanies this distribution. The full text of the license may be found at | |
8 | * http://opensource.org/licenses/bsd-license.php | |
9 | * | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
12 | * | |
13 | **/ | |
14 | ||
15 | #include <Library/IoLib.h> | |
16 | #include <Library/ArmTrustZoneLib.h> | |
17 | #include <Library/ArmPlatformLib.h> | |
18 | #include <Library/DebugLib.h> | |
19 | #include <Library/PcdLib.h> | |
20 | #include <Drivers/PL341Dmc.h> | |
8e06b586 | 21 | #include <Drivers/PL301Axi.h> |
22 | #include <Library/L2X0CacheLib.h> | |
2637d1ef | 23 | #include <Library/SerialPortLib.h> |
24 | ||
25 | #define SerialPrint(txt) SerialPortWrite (txt, AsciiStrLen(txt)+1); | |
1d5d0ae9 | 26 | |
27 | // DDR2 timings | |
28 | struct pl341_dmc_config ddr_timings = { | |
29 | .base = ARM_VE_DMC_BASE, | |
30 | .has_qos = 1, | |
31 | .refresh_prd = 0x3D0, | |
32 | .cas_latency = 0x8, | |
33 | .write_latency = 0x3, | |
34 | .t_mrd = 0x2, | |
35 | .t_ras = 0xA, | |
36 | .t_rc = 0xE, | |
37 | .t_rcd = 0x104, | |
38 | .t_rfc = 0x2f32, | |
39 | .t_rp = 0x14, | |
40 | .t_rrd = 0x2, | |
41 | .t_wr = 0x4, | |
42 | .t_wtr = 0x2, | |
43 | .t_xp = 0x2, | |
44 | .t_xsr = 0xC8, | |
45 | .t_esr = 0x14, | |
46 | .memory_cfg = DMC_MEMORY_CONFIG_ACTIVE_CHIP_1 | DMC_MEMORY_CONFIG_BURST_4 | | |
47 | DMC_MEMORY_CONFIG_ROW_ADDRESS_15 | DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10, | |
48 | .memory_cfg2 = DMC_MEMORY_CFG2_DQM_INIT | DMC_MEMORY_CFG2_CKE_INIT | | |
49 | DMC_MEMORY_CFG2_BANK_BITS_3 | DMC_MEMORY_CFG2_MEM_WIDTH_32, | |
50 | .memory_cfg3 = 0x00000001, | |
51 | .chip_cfg0 = 0x00010000, | |
52 | .t_faw = 0x00000A0D, | |
53 | }; | |
54 | ||
55 | /** | |
56 | Return if Trustzone is supported by your platform | |
57 | ||
58 | A non-zero value must be returned if you want to support a Secure World on your platform. | |
59 | ArmVExpressTrustzoneInit() will later set up the secure regions. | |
60 | This function can return 0 even if Trustzone is supported by your processor. In this case, | |
61 | the platform will continue to run in Secure World. | |
62 | ||
63 | @return A non-zero value if Trustzone supported. | |
64 | ||
65 | **/ | |
66 | UINTN ArmPlatformTrustzoneSupported(VOID) { | |
67 | return (MmioRead32(ARM_VE_SYS_CFGRW1_REG) & ARM_VE_CFGRW1_TZASC_EN_BIT_MASK); | |
68 | } | |
69 | ||
70 | /** | |
71 | Initialize the Secure peripherals and memory regions | |
72 | ||
73 | If Trustzone is supported by your platform then this function makes the required initialization | |
74 | of the secure peripherals and memory regions. | |
75 | ||
76 | **/ | |
77 | VOID ArmPlatformTrustzoneInit(VOID) { | |
78 | // | |
79 | // Setup TZ Protection Controller | |
80 | // | |
81 | ||
82 | // Set Non Secure access for all devices | |
83 | TZPCSetDecProtBits(ARM_VE_TZPC_BASE, TZPC_DECPROT_0, 0xFFFFFFFF); | |
84 | TZPCSetDecProtBits(ARM_VE_TZPC_BASE, TZPC_DECPROT_1, 0xFFFFFFFF); | |
85 | TZPCSetDecProtBits(ARM_VE_TZPC_BASE, TZPC_DECPROT_2, 0xFFFFFFFF); | |
86 | ||
87 | // Remove Non secure access to secure devices | |
88 | TZPCClearDecProtBits(ARM_VE_TZPC_BASE, TZPC_DECPROT_0, | |
89 | ARM_VE_DECPROT_BIT_TZPC | ARM_VE_DECPROT_BIT_DMC_TZASC | ARM_VE_DECPROT_BIT_NMC_TZASC | ARM_VE_DECPROT_BIT_SMC_TZASC); | |
90 | ||
91 | TZPCClearDecProtBits(ARM_VE_TZPC_BASE, TZPC_DECPROT_2, | |
92 | ARM_VE_DECPROT_BIT_EXT_MAST_TZ | ARM_VE_DECPROT_BIT_DMC_TZASC_LOCK | ARM_VE_DECPROT_BIT_NMC_TZASC_LOCK | ARM_VE_DECPROT_BIT_SMC_TZASC_LOCK); | |
93 | ||
94 | ||
95 | // | |
96 | // Setup TZ Address Space Controller for the SMC. Create 5 Non Secure regions (NOR0, NOR1, SRAM, SMC Peripheral regions) | |
97 | // | |
98 | ||
99 | // NOR Flash 0 non secure (BootMon) | |
100 | TZASCSetRegion(ARM_VE_TZASC_BASE,1,TZASC_REGION_ENABLED, | |
101 | ARM_VE_SMB_NOR0_BASE,0, | |
102 | TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW); | |
103 | ||
104 | // NOR Flash 1. The first half of the NOR Flash1 must be secure for the secure firmware (sec_uefi.bin) | |
105 | #if EDK2_ARMVE_SECURE_SYSTEM | |
106 | //Note: Your OS Kernel must be aware of the secure regions before to enable this region | |
107 | TZASCSetRegion(ARM_VE_TZASC_BASE,2,TZASC_REGION_ENABLED, | |
108 | ARM_VE_SMB_NOR1_BASE + SIZE_32MB,0, | |
109 | TZASC_REGION_SIZE_32MB, TZASC_REGION_SECURITY_NSRW); | |
110 | #else | |
111 | TZASCSetRegion(ARM_VE_TZASC_BASE,2,TZASC_REGION_ENABLED, | |
112 | ARM_VE_SMB_NOR1_BASE,0, | |
113 | TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW); | |
114 | #endif | |
115 | ||
116 | // Base of SRAM. Only half of SRAM in Non Secure world | |
117 | // First half non secure (16MB) + Second Half secure (16MB) = 32MB of SRAM | |
118 | #if EDK2_ARMVE_SECURE_SYSTEM | |
119 | //Note: Your OS Kernel must be aware of the secure regions before to enable this region | |
120 | TZASCSetRegion(ARM_VE_TZASC_BASE,3,TZASC_REGION_ENABLED, | |
121 | ARM_VE_SMB_SRAM_BASE,0, | |
122 | TZASC_REGION_SIZE_16MB, TZASC_REGION_SECURITY_NSRW); | |
123 | #else | |
124 | TZASCSetRegion(ARM_VE_TZASC_BASE,3,TZASC_REGION_ENABLED, | |
125 | ARM_VE_SMB_SRAM_BASE,0, | |
126 | TZASC_REGION_SIZE_32MB, TZASC_REGION_SECURITY_NSRW); | |
127 | #endif | |
128 | ||
129 | // Memory Mapped Peripherals. All in non secure world | |
130 | TZASCSetRegion(ARM_VE_TZASC_BASE,4,TZASC_REGION_ENABLED, | |
131 | ARM_VE_SMB_PERIPH_BASE,0, | |
132 | TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW); | |
133 | ||
134 | // MotherBoard Peripherals and On-chip peripherals. | |
135 | TZASCSetRegion(ARM_VE_TZASC_BASE,5,TZASC_REGION_ENABLED, | |
136 | ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE,0, | |
137 | TZASC_REGION_SIZE_256MB, TZASC_REGION_SECURITY_NSRW); | |
138 | } | |
139 | ||
a534d714 | 140 | /** |
141 | Return the current Boot Mode | |
142 | ||
143 | This function returns the boot reason on the platform | |
144 | ||
145 | @return Return the current Boot Mode of the platform | |
146 | ||
147 | **/ | |
148 | EFI_BOOT_MODE | |
149 | ArmPlatformGetBootMode ( | |
150 | VOID | |
151 | ) | |
152 | { | |
153 | return BOOT_WITH_FULL_CONFIGURATION; | |
154 | } | |
155 | ||
1d5d0ae9 | 156 | /** |
157 | Remap the memory at 0x0 | |
158 | ||
159 | Some platform requires or gives the ability to remap the memory at the address 0x0. | |
160 | This function can do nothing if this feature is not relevant to your platform. | |
161 | ||
162 | **/ | |
163 | VOID ArmPlatformBootRemapping(VOID) { | |
164 | UINT32 val32 = MmioRead32(ARM_VE_SYS_CFGRW1_REG); //Scc - CFGRW1 | |
165 | // we remap the DRAM to 0x0 | |
166 | MmioWrite32(ARM_VE_SYS_CFGRW1_REG, (val32 & 0x0FFFFFFF) | ARM_VE_CFGRW1_REMAP_DRAM); | |
167 | } | |
168 | ||
8e06b586 | 169 | /** |
170 | Initialize controllers that must setup at the early stage | |
171 | ||
172 | Some peripherals must be initialized in Secure World. | |
173 | For example, some L2x0 requires to be initialized in Secure World | |
174 | ||
175 | **/ | |
176 | VOID | |
177 | ArmPlatformInitialize ( | |
178 | VOID | |
179 | ) { | |
180 | // The L2x0 controller must be intialize in Secure World | |
181 | L2x0CacheInit(PcdGet32(PcdL2x0ControllerBase), FALSE); | |
182 | } | |
183 | ||
1d5d0ae9 | 184 | /** |
185 | Initialize the system (or sometimes called permanent) memory | |
186 | ||
187 | This memory is generally represented by the DRAM. | |
188 | ||
189 | **/ | |
190 | VOID ArmPlatformInitializeSystemMemory(VOID) { | |
191 | PL341DmcInit(&ddr_timings); | |
192 | PL301AxiInit(ARM_VE_FAXI_BASE); | |
193 | } |