[mirror_edk2.git] / ArmPlatformPkg / ArmVExpressPkg / Library / ArmVExpressLibRTSM / Arm / RTSMHelper.S

#\r
#  Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
#  \r
#  This program and the accompanying materials                          \r
#  are licensed and made available under the terms and conditions of the BSD License         \r
#  which accompanies this distribution.  The full text of the license may be found at        \r
#  http://opensource.org/licenses/bsd-license.php\r
#\r
#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
#\r
#\r
\r
#include <AsmMacroIoLib.h>\r
#include <Base.h>\r
#include <Library/PcdLib.h>\r
#include <AutoGen.h>\r
\r
#include <Chipset/ArmCortexA9.h>\r
\r
.text\r
.align 2\r
\r
GCC_ASM_EXPORT(ArmGetCpuCountPerCluster)\r
GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)\r
\r
GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore)\r
GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)\r
\r
# IN None\r
# OUT r0 = SCU Base Address\r
ASM_PFX(ArmGetScuBaseAddress):\r
  # Read Configuration Base Address Register. ArmCBar cannot be called to get\r
  # the Configuration BAR as a stack is not necessary setup. The SCU is at the\r
  # offset 0x0000 from the Private Memory Region.\r
  mrc   p15, 4, r0, c15, c0, 0\r
  bx  lr\r
\r
# IN None\r
# OUT r0 = number of cores present in the system\r
ASM_PFX(ArmGetCpuCountPerCluster):\r
  stmfd SP!, {r1-r2}\r
\r
  # Read CP15 MIDR\r
  mrc   p15, 0, r1, c0, c0, 0\r
\r
  # Check if the CPU is A15\r
  mov   r1, r1, LSR #4\r
  LoadConstantToReg (ARM_CPU_TYPE_MASK, r0)\r
  and   r1, r1, r0\r
\r
  LoadConstantToReg (ARM_CPU_TYPE_A15, r0)\r
  cmp   r1, r0\r
  beq   _Read_cp15_reg\r
\r
_CPU_is_not_A15:\r
  mov   r2, lr                           @ Save link register\r
  bl    ArmGetScuBaseAddress             @ Read SCU Base Address\r
  mov   lr, r2                           @ Restore link register val\r
  ldr   r0, [r0, #A9_SCU_CONFIG_OFFSET]     @ Read SCU Config reg to get CPU count\r
  b     _Return\r
\r
_Read_cp15_reg:\r
  mrc   p15, 1, r0, c9, c0, 2            @ Read C9 register of CP15 to get CPU count\r
  lsr   r0, #24\r
\r
_Return:\r
  and   r0, r0, #3\r
  # Add '1' to the number of CPU on the Cluster\r
  add   r0, r0, #1\r
  ldmfd SP!, {r1-r2}\r
  bx lr\r
\r
//UINTN\r
//ArmPlatformIsPrimaryCore (\r
//  IN UINTN MpId\r
//  );\r
ASM_PFX(ArmPlatformIsPrimaryCore):\r
  LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1)\r
  ldr   r1, [r1]\r
  and   r0, r0, r1\r
  LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r1)\r
  ldr   r1, [r1]\r
  cmp   r0, r1\r
  moveq r0, #1\r
  movne r0, #0\r
  bx 	lr\r
\r
ASM_FUNCTION_REMOVE_IF_UNREFERENCED \r
Commit	Line	Data
88d4f51d	1	#\r
bebda7ce	2	# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
88d4f51d	3	# \r
	4	# This program and the accompanying materials \r
	5	# are licensed and made available under the terms and conditions of the BSD License \r
	6	# which accompanies this distribution. The full text of the license may be found at \r
bebda7ce	7	# http://opensource.org/licenses/bsd-license.php\r
88d4f51d	8	#\r
	9	# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	10	# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
	11	#\r
	12	#\r
	13	\r
	14	#include <AsmMacroIoLib.h>\r
	15	#include <Base.h>\r
	16	#include <Library/PcdLib.h>\r
	17	#include <AutoGen.h>\r
88d4f51d	18	\r
	19	#include <Chipset/ArmCortexA9.h>\r
	20	\r
	21	.text\r
	22	.align 2\r
	23	\r
	24	GCC_ASM_EXPORT(ArmGetCpuCountPerCluster)\r
bebda7ce	25	GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)\r
	26	\r
	27	GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore)\r
	28	GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)\r
88d4f51d	29	\r
	30	# IN None\r
	31	# OUT r0 = SCU Base Address\r
	32	ASM_PFX(ArmGetScuBaseAddress):\r
	33	# Read Configuration Base Address Register. ArmCBar cannot be called to get\r
	34	# the Configuration BAR as a stack is not necessary setup. The SCU is at the\r
	35	# offset 0x0000 from the Private Memory Region.\r
	36	mrc p15, 4, r0, c15, c0, 0\r
	37	bx lr\r
	38	\r
	39	# IN None\r
	40	# OUT r0 = number of cores present in the system\r
	41	ASM_PFX(ArmGetCpuCountPerCluster):\r
	42	stmfd SP!, {r1-r2}\r
	43	\r
	44	# Read CP15 MIDR\r
	45	mrc p15, 0, r1, c0, c0, 0\r
	46	\r
	47	# Check if the CPU is A15\r
	48	mov r1, r1, LSR #4\r
	49	LoadConstantToReg (ARM_CPU_TYPE_MASK, r0)\r
	50	and r1, r1, r0\r
	51	\r
	52	LoadConstantToReg (ARM_CPU_TYPE_A15, r0)\r
	53	cmp r1, r0\r
	54	beq _Read_cp15_reg\r
	55	\r
	56	_CPU_is_not_A15:\r
	57	mov r2, lr @ Save link register\r
	58	bl ArmGetScuBaseAddress @ Read SCU Base Address\r
	59	mov lr, r2 @ Restore link register val\r
	60	ldr r0, [r0, #A9_SCU_CONFIG_OFFSET] @ Read SCU Config reg to get CPU count\r
	61	b _Return\r
	62	\r
	63	_Read_cp15_reg:\r
	64	mrc p15, 1, r0, c9, c0, 2 @ Read C9 register of CP15 to get CPU count\r
	65	lsr r0, #24\r
	66	\r
	67	_Return:\r
	68	and r0, r0, #3\r
	69	# Add '1' to the number of CPU on the Cluster\r
	70	add r0, r0, #1\r
	71	ldmfd SP!, {r1-r2}\r
	72	bx lr\r
	73	\r
bebda7ce	74	//UINTN\r
	75	//ArmPlatformIsPrimaryCore (\r
	76	// IN UINTN MpId\r
	77	// );\r
	78	ASM_PFX(ArmPlatformIsPrimaryCore):\r
	79	LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1)\r
	80	ldr r1, [r1]\r
	81	and r0, r0, r1\r
	82	LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r1)\r
	83	ldr r1, [r1]\r
	84	cmp r0, r1\r
	85	moveq r0, #1\r
	86	movne r0, #0\r
	87	bx lr\r
	88	\r
88d4f51d	89	ASM_FUNCTION_REMOVE_IF_UNREFERENCED \r