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88d4f51d | 1 | //\r |
2d45f194 | 2 | // Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r |
88d4f51d | 3 | //\r |
3402aac7 RC |
4 | // This program and the accompanying materials\r |
5 | // are licensed and made available under the terms and conditions of the BSD License\r | |
6 | // which accompanies this distribution. The full text of the license may be found at\r | |
7 | // http://opensource.org/licenses/bsd-license.php\r | |
8 | //\r | |
9 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
10 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
88d4f51d | 11 | //\r |
12 | //\r | |
13 | \r | |
14 | #include <AsmMacroIoLib.h>\r | |
15 | #include <Base.h>\r | |
2d45f194 | 16 | #include <Library/ArmLib.h>\r |
88d4f51d | 17 | #include <Library/PcdLib.h>\r |
18 | \r | |
19 | #include <Chipset/ArmCortexA9.h>\r | |
20 | \r | |
21 | #include <AutoGen.h>\r | |
22 | \r | |
23 | INCLUDE AsmMacroIoLib.inc\r | |
24 | \r | |
b5a57223 | 25 | EXPORT ArmPlatformPeiBootAction\r |
88d4f51d | 26 | EXPORT ArmGetCpuCountPerCluster\r |
bebda7ce | 27 | EXPORT ArmPlatformIsPrimaryCore\r |
d05ca26c | 28 | EXPORT ArmPlatformGetPrimaryCoreMpId\r |
2d45f194 | 29 | EXPORT ArmPlatformGetCorePosition\r |
bebda7ce | 30 | \r |
2d45f194 | 31 | IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCore\r |
32 | IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCoreMask\r | |
bebda7ce | 33 | \r |
88d4f51d | 34 | AREA RTSMHelper, CODE, READONLY\r |
35 | \r | |
b5a57223 | 36 | ArmPlatformPeiBootAction FUNCTION\r |
37 | bx lr\r | |
38 | ENDFUNC\r | |
39 | \r | |
88d4f51d | 40 | // IN None\r |
41 | // OUT r0 = SCU Base Address\r | |
bebda7ce | 42 | ArmGetScuBaseAddress FUNCTION\r |
88d4f51d | 43 | // Read Configuration Base Address Register. ArmCBar cannot be called to get\r |
44 | // the Configuration BAR as a stack is not necessary setup. The SCU is at the\r | |
45 | // offset 0x0000 from the Private Memory Region.\r | |
46 | mrc p15, 4, r0, c15, c0, 0\r | |
47 | bx lr\r | |
bebda7ce | 48 | ENDFUNC\r |
88d4f51d | 49 | \r |
d05ca26c | 50 | //UINTN\r |
51 | //ArmPlatformGetPrimaryCoreMpId (\r | |
52 | // VOID\r | |
53 | // );\r | |
54 | ArmPlatformGetPrimaryCoreMpId FUNCTION\r | |
99267097 | 55 | LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r0)\r |
d05ca26c | 56 | ldr r0, [r0]\r |
57 | bx lr\r | |
58 | ENDFUNC\r | |
59 | \r | |
88d4f51d | 60 | // IN None\r |
61 | // OUT r0 = number of cores present in the system\r | |
bebda7ce | 62 | ArmGetCpuCountPerCluster FUNCTION\r |
88d4f51d | 63 | stmfd SP!, {r1-r2}\r |
64 | \r | |
65 | // Read CP15 MIDR\r | |
66 | mrc p15, 0, r1, c0, c0, 0\r | |
67 | \r | |
68 | // Check if the CPU is A15\r | |
69 | mov r1, r1, LSR #4\r | |
70 | mov r0, #ARM_CPU_TYPE_MASK\r | |
71 | and r1, r1, r0\r | |
72 | \r | |
73 | mov r0, #ARM_CPU_TYPE_A15\r | |
74 | cmp r1, r0\r | |
75 | beq _Read_cp15_reg\r | |
76 | \r | |
77 | _CPU_is_not_A15\r | |
78 | mov r2, lr ; Save link register\r | |
79 | bl ArmGetScuBaseAddress ; Read SCU Base Address\r | |
80 | mov lr, r2 ; Restore link register val\r | |
81 | ldr r0, [r0, #A9_SCU_CONFIG_OFFSET] ; Read SCU Config reg to get CPU count\r | |
82 | b _Return\r | |
83 | \r | |
84 | _Read_cp15_reg\r | |
85 | mrc p15, 1, r0, c9, c0, 2 ; Read C9 register of CP15 to get CPU count\r | |
86 | lsr r0, #24\r | |
87 | \r | |
88 | \r | |
89 | _Return\r | |
90 | and r0, r0, #3\r | |
91 | // Add '1' to the number of CPU on the Cluster\r | |
92 | add r0, r0, #1\r | |
93 | ldmfd SP!, {r1-r2}\r | |
94 | bx lr\r | |
bebda7ce | 95 | ENDFUNC\r |
96 | \r | |
97 | //UINTN\r | |
98 | //ArmPlatformIsPrimaryCore (\r | |
99 | // IN UINTN MpId\r | |
100 | // );\r | |
101 | ArmPlatformIsPrimaryCore FUNCTION\r | |
102 | LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1)\r | |
103 | ldr r1, [r1]\r | |
104 | and r0, r0, r1\r | |
105 | LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r1)\r | |
106 | ldr r1, [r1]\r | |
107 | cmp r0, r1\r | |
108 | moveq r0, #1\r | |
109 | movne r0, #0\r | |
110 | bx lr\r | |
111 | ENDFUNC\r | |
88d4f51d | 112 | \r |
2d45f194 | 113 | //UINTN\r |
114 | //ArmPlatformGetCorePosition (\r | |
115 | // IN UINTN MpId\r | |
116 | // );\r | |
117 | ArmPlatformGetCorePosition FUNCTION\r | |
118 | and r1, r0, #ARM_CORE_MASK\r | |
119 | and r0, r0, #ARM_CLUSTER_MASK\r | |
120 | add r0, r1, r0, LSR #7\r | |
121 | bx lr\r | |
122 | ENDFUNC\r | |
123 | \r | |
88d4f51d | 124 | END\r |