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88d4f51d | 1 | //\r |
bebda7ce | 2 | // Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r |
88d4f51d | 3 | // \r |
4 | // This program and the accompanying materials \r | |
5 | // are licensed and made available under the terms and conditions of the BSD License \r | |
6 | // which accompanies this distribution. The full text of the license may be found at \r | |
7 | // http://opensource.org/licenses/bsd-license.php \r | |
8 | //\r | |
9 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
10 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
11 | //\r | |
12 | //\r | |
13 | \r | |
14 | #include <AsmMacroIoLib.h>\r | |
15 | #include <Base.h>\r | |
16 | #include <Library/PcdLib.h>\r | |
17 | \r | |
18 | #include <Chipset/ArmCortexA9.h>\r | |
19 | \r | |
20 | #include <AutoGen.h>\r | |
21 | \r | |
22 | INCLUDE AsmMacroIoLib.inc\r | |
23 | \r | |
24 | EXPORT ArmGetCpuCountPerCluster\r | |
bebda7ce | 25 | EXPORT ArmPlatformIsPrimaryCore\r |
26 | \r | |
27 | IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCore\r | |
28 | IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCoreMask\r | |
29 | \r | |
88d4f51d | 30 | AREA RTSMHelper, CODE, READONLY\r |
31 | \r | |
32 | // IN None\r | |
33 | // OUT r0 = SCU Base Address\r | |
bebda7ce | 34 | ArmGetScuBaseAddress FUNCTION\r |
88d4f51d | 35 | // Read Configuration Base Address Register. ArmCBar cannot be called to get\r |
36 | // the Configuration BAR as a stack is not necessary setup. The SCU is at the\r | |
37 | // offset 0x0000 from the Private Memory Region.\r | |
38 | mrc p15, 4, r0, c15, c0, 0\r | |
39 | bx lr\r | |
bebda7ce | 40 | ENDFUNC\r |
88d4f51d | 41 | \r |
42 | // IN None\r | |
43 | // OUT r0 = number of cores present in the system\r | |
bebda7ce | 44 | ArmGetCpuCountPerCluster FUNCTION\r |
88d4f51d | 45 | stmfd SP!, {r1-r2}\r |
46 | \r | |
47 | // Read CP15 MIDR\r | |
48 | mrc p15, 0, r1, c0, c0, 0\r | |
49 | \r | |
50 | // Check if the CPU is A15\r | |
51 | mov r1, r1, LSR #4\r | |
52 | mov r0, #ARM_CPU_TYPE_MASK\r | |
53 | and r1, r1, r0\r | |
54 | \r | |
55 | mov r0, #ARM_CPU_TYPE_A15\r | |
56 | cmp r1, r0\r | |
57 | beq _Read_cp15_reg\r | |
58 | \r | |
59 | _CPU_is_not_A15\r | |
60 | mov r2, lr ; Save link register\r | |
61 | bl ArmGetScuBaseAddress ; Read SCU Base Address\r | |
62 | mov lr, r2 ; Restore link register val\r | |
63 | ldr r0, [r0, #A9_SCU_CONFIG_OFFSET] ; Read SCU Config reg to get CPU count\r | |
64 | b _Return\r | |
65 | \r | |
66 | _Read_cp15_reg\r | |
67 | mrc p15, 1, r0, c9, c0, 2 ; Read C9 register of CP15 to get CPU count\r | |
68 | lsr r0, #24\r | |
69 | \r | |
70 | \r | |
71 | _Return\r | |
72 | and r0, r0, #3\r | |
73 | // Add '1' to the number of CPU on the Cluster\r | |
74 | add r0, r0, #1\r | |
75 | ldmfd SP!, {r1-r2}\r | |
76 | bx lr\r | |
bebda7ce | 77 | ENDFUNC\r |
78 | \r | |
79 | //UINTN\r | |
80 | //ArmPlatformIsPrimaryCore (\r | |
81 | // IN UINTN MpId\r | |
82 | // );\r | |
83 | ArmPlatformIsPrimaryCore FUNCTION\r | |
84 | LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1)\r | |
85 | ldr r1, [r1]\r | |
86 | and r0, r0, r1\r | |
87 | LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r1)\r | |
88 | ldr r1, [r1]\r | |
89 | cmp r0, r1\r | |
90 | moveq r0, #1\r | |
91 | movne r0, #0\r | |
92 | bx lr\r | |
93 | ENDFUNC\r | |
88d4f51d | 94 | \r |
95 | END\r |