]>
Commit | Line | Data |
---|---|---|
c52e2dca | 1 | //\r |
e314d564 | 2 | // Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r |
c52e2dca | 3 | //\r |
4 | // This program and the accompanying materials\r | |
5 | // are licensed and made available under the terms and conditions of the BSD License\r | |
6 | // which accompanies this distribution. The full text of the license may be found at\r | |
7 | // http://opensource.org/licenses/bsd-license.php\r | |
8 | //\r | |
9 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
10 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
11 | //\r | |
12 | //\r | |
13 | \r | |
14 | #include <AsmMacroIoLib.h>\r | |
c52e2dca | 15 | #include <Library/ArmPlatformLib.h>\r |
16 | #include <Drivers/PL35xSmc.h>\r | |
17 | #include <ArmPlatform.h>\r | |
c52e2dca | 18 | \r |
19 | //\r | |
20 | // For each Chip Select: ChipSelect / SetCycle / SetOpMode\r | |
21 | //\r | |
22 | VersatileExpressSmcConfiguration:\r | |
23 | // NOR Flash 0\r | |
24 | .word PL350_SMC_DIRECT_CMD_ADDR_CS(0)\r | |
3723a71a | 25 | .word PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) | PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) | PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) | PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) | PL350_SMC_SET_CYCLE_NAND_T_AR(0x1)\r |
26 | .word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 | PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT | PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT | PL350_SMC_SET_OPMODE_SET_ADV\r | |
c52e2dca | 27 | \r |
28 | // NOR Flash 1\r | |
29 | .word PL350_SMC_DIRECT_CMD_ADDR_CS(4)\r | |
3723a71a | 30 | .word PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) | PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) | PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) | PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) | PL350_SMC_SET_CYCLE_NAND_T_AR(0x1)\r |
31 | .word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 | PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT | PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT | PL350_SMC_SET_OPMODE_SET_ADV\r | |
c52e2dca | 32 | \r |
33 | // SRAM\r | |
34 | .word PL350_SMC_DIRECT_CMD_ADDR_CS(2)\r | |
3723a71a | 35 | .word PL350_SMC_SET_CYCLE_SRAM_T_RC(0x8) | PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) | PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) | PL350_SMC_SET_CYCLE_SRAM_T_WP(0x6) | PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) | PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1)\r |
36 | .word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 | PL350_SMC_SET_OPMODE_SET_ADV\r | |
c52e2dca | 37 | \r |
38 | // Usb/Eth/VRAM\r | |
39 | .word PL350_SMC_DIRECT_CMD_ADDR_CS(3)\r | |
3723a71a | 40 | .word PL350_SMC_SET_CYCLE_SRAM_T_RC(0xA) | PL350_SMC_SET_CYCLE_SRAM_T_WC(0xA) | PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x2) | PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) | PL350_SMC_SET_CYCLE_SRAM_T_PC(0x3) | PL350_SMC_SET_CYCLE_SRAM_T_TR(0x6)\r |
41 | .word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 | PL350_SMC_SET_OPMODE_SET_RD_SYNC | PL350_SMC_SET_OPMODE_SET_WR_SYNC\r | |
c52e2dca | 42 | \r |
43 | // Memory Mapped Peripherals\r | |
44 | .word PL350_SMC_DIRECT_CMD_ADDR_CS(7)\r | |
3723a71a | 45 | .word PL350_SMC_SET_CYCLE_SRAM_T_RC(0x6) | PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) | PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) | PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) | PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) | PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1)\r |
46 | .word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 | PL350_SMC_SET_OPMODE_SET_RD_SYNC | PL350_SMC_SET_OPMODE_SET_WR_SYNC\r | |
c52e2dca | 47 | \r |
48 | // VRAM\r | |
49 | .word PL350_SMC_DIRECT_CMD_ADDR_CS(1)\r | |
50 | .word 0x00049249\r | |
3723a71a | 51 | .word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 | PL350_SMC_SET_OPMODE_SET_RD_SYNC | PL350_SMC_SET_OPMODE_SET_WR_SYNC\r |
c52e2dca | 52 | VersatileExpressSmcConfigurationEnd:\r |
53 | \r | |
44e272fd | 54 | /**\r |
55 | Call at the beginning of the platform boot up\r | |
56 | \r | |
57 | This function allows the firmware platform to do extra actions at the early\r | |
58 | stage of the platform power up.\r | |
59 | \r | |
60 | Note: This function must be implemented in assembler as there is no stack set up yet\r | |
61 | \r | |
62 | **/\r | |
04209b53 | 63 | ASM_FUNC(ArmPlatformSecBootAction)\r |
44e272fd | 64 | bx lr\r |
65 | \r | |
c52e2dca | 66 | /**\r |
67 | Initialize the memory where the initial stacks will reside\r | |
68 | \r | |
69 | This memory can contain the initial stacks (Secure and Secure Monitor stacks).\r | |
70 | In some platform, this region is already initialized and the implementation of this function can\r | |
71 | do nothing. This memory can also represent the Secure RAM.\r | |
72 | This function is called before the satck has been set up. Its implementation must ensure the stack\r | |
73 | pointer is not used (probably required to use assembly language)\r | |
74 | \r | |
75 | **/\r | |
04209b53 | 76 | ASM_FUNC(ArmPlatformSecBootMemoryInit)\r |
c52e2dca | 77 | mov r5, lr\r |
78 | \r | |
79 | //\r | |
80 | // Initialize PL354 SMC\r | |
81 | //\r | |
04209b53 AB |
82 | MOV32 (r1, ARM_VE_SMC_CTRL_BASE)\r |
83 | MOV32 (r2, VersatileExpressSmcConfiguration)\r | |
84 | MOV32 (r3, VersatileExpressSmcConfigurationEnd)\r | |
c52e2dca | 85 | blx ASM_PFX(PL35xSmcInitialize)\r |
86 | \r | |
87 | //\r | |
88 | // Page mode setup for VRAM\r | |
89 | //\r | |
04209b53 | 90 | MOV32 (r2, VRAM_MOTHERBOARD_BASE)\r |
c52e2dca | 91 | \r |
92 | // Read current state\r | |
93 | ldr r0, [r2, #0]\r | |
94 | ldr r0, [r2, #0]\r | |
95 | ldr r0, = 0x00000000\r | |
96 | str r0, [r2, #0]\r | |
97 | ldr r0, [r2, #0]\r | |
98 | \r | |
99 | // Enable page mode\r | |
100 | ldr r0, [r2, #0]\r | |
101 | ldr r0, [r2, #0]\r | |
102 | ldr r0, = 0x00000000\r | |
103 | str r0, [r2, #0]\r | |
04209b53 | 104 | ldr r0, = 0x00900090\r |
c52e2dca | 105 | str r0, [r2, #0]\r |
106 | \r | |
107 | // Confirm page mode enabled\r | |
108 | ldr r0, [r2, #0]\r | |
109 | ldr r0, [r2, #0]\r | |
110 | ldr r0, = 0x00000000\r | |
111 | str r0, [r2, #0]\r | |
112 | ldr r0, [r2, #0]\r | |
113 | \r | |
114 | bx r5\r |