ArmPlatformPkg/ArmVExpressSecLibRTSM: Only use extended name of system registers...
[mirror_edk2.git] / ArmPlatformPkg / ArmVExpressPkg / Library / ArmVExpressSecLibRTSM / AArch64 / GicV3.S
CommitLineData
75f63034 1//\r
51ad04cb 2// Copyright (c) 2013-2014, ARM Limited. All rights reserved.\r
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3//\r
4// This program and the accompanying materials\r
5// are licensed and made available under the terms and conditions of the BSD License\r
6// which accompanies this distribution. The full text of the license may be found at\r
7// http://opensource.org/licenses/bsd-license.php\r
8//\r
9// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
10// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
11//\r
12//\r
13\r
51ad04cb 14#include <AsmMacroIoLibV8.h>\r
75f63034 15\r
e6911838 16#ifndef __clang__\r
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17// Register definitions used by GCC for GICv3 access.\r
18// These are defined by ARMCC, so keep them in the GCC specific code for now.\r
19#define ICC_SRE_EL2 S3_4_C12_C9_5\r
20#define ICC_SRE_EL3 S3_6_C12_C12_5\r
21#define ICC_CTLR_EL1 S3_0_C12_C12_4\r
22#define ICC_CTLR_EL3 S3_6_C12_C12_4\r
23#define ICC_PMR_EL1 S3_0_C4_C6_0\r
e6911838 24#endif\r
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25\r
26.text\r
27.align 3\r
28\r
29GCC_ASM_EXPORT(InitializeGicV3)\r
30\r
31/* Initialize GICv3 to expose it as a GICv2 as UEFI does not support GICv3 yet */\r
32ASM_PFX(InitializeGicV3):\r
33 // We have a GICv3. UEFI still uses the GICv2 mode. We must do enough setup\r
34 // to allow Linux to use GICv3 if it chooses.\r
35\r
36 // In order to setup NS side we need to enable it first.\r
37 mrs x0, scr_el3\r
38 orr x0, x0, #1\r
39 msr scr_el3, x0\r
40\r
41 // Enable SRE at EL3 and ICC_SRE_EL2 access\r
42 mov x0, #((1 << 3) | (1 << 0)) // Enable | SRE\r
43 mrs x1, ICC_SRE_EL3\r
44 orr x1, x1, x0\r
45 msr ICC_SRE_EL3, x1\r
46 isb\r
47\r
48 // Enable SRE at EL2 and ICC_SRE_EL1 access..\r
49 mrs x1, ICC_SRE_EL2\r
50 orr x1, x1, x0\r
51 msr ICC_SRE_EL2, x1\r
52 isb\r
53\r
54 // Configure CPU interface\r
55 msr ICC_CTLR_EL3, xzr\r
56 isb\r
57 msr ICC_CTLR_EL1, xzr\r
58 isb\r
59\r
60 // The MemoryMap view and Register view may not be consistent, So Set PMR again.\r
61 mov w1, #1 << 7 // allow NS access to GICC_PMR\r
62 msr ICC_PMR_EL1, x1\r
63 isb\r
64\r
65 // Remove the SCR.NS bit\r
66 mrs x0, scr_el3\r
67 bic x0, x0, #1\r
68 msr scr_el3, x0\r
69 ret\r