| e314d564 |
1 | //\r |
| 2 | // Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r |
| 3 | // \r |
| 4 | // This program and the accompanying materials \r |
| 5 | // are licensed and made available under the terms and conditions of the BSD License \r |
| 6 | // which accompanies this distribution. The full text of the license may be found at \r |
| 7 | // http://opensource.org/licenses/bsd-license.php \r |
| 8 | //\r |
| 9 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r |
| 10 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r |
| 11 | //\r |
| 12 | //\r |
| 13 | \r |
| 14 | #include <AsmMacroIoLib.h>\r |
| 15 | #include <Base.h>\r |
| 16 | #include <Library/PcdLib.h>\r |
| 17 | \r |
| 18 | #include <Chipset/ArmCortexA9.h>\r |
| 19 | \r |
| 20 | #include <AutoGen.h>\r |
| 21 | \r |
| 22 | INCLUDE AsmMacroIoLib.inc\r |
| 23 | \r |
| 24 | EXPORT ArmGetCpuCountPerCluster\r |
| 25 | \r |
| 26 | AREA RTSMHelper, CODE, READONLY\r |
| 27 | \r |
| 28 | // IN None\r |
| 29 | // OUT r0 = SCU Base Address\r |
| 30 | ArmGetScuBaseAddress\r |
| 31 | // Read Configuration Base Address Register. ArmCBar cannot be called to get\r |
| 32 | // the Configuration BAR as a stack is not necessary setup. The SCU is at the\r |
| 33 | // offset 0x0000 from the Private Memory Region.\r |
| 34 | mrc p15, 4, r0, c15, c0, 0\r |
| 35 | bx lr\r |
| 36 | \r |
| 37 | // IN None\r |
| 38 | // OUT r0 = number of cores present in the system\r |
| 39 | ArmGetCpuCountPerCluster\r |
| 40 | stmfd SP!, {r1-r2}\r |
| 41 | \r |
| 42 | // Read CP15 MIDR\r |
| 43 | mrc p15, 0, r1, c0, c0, 0\r |
| 44 | \r |
| 45 | // Check if the CPU is A15\r |
| 46 | mov r1, r1, LSR #4\r |
| 47 | mov r0, #ARM_CPU_TYPE_MASK\r |
| 48 | and r1, r1, r0\r |
| 49 | \r |
| 50 | mov r0, #ARM_CPU_TYPE_A15\r |
| 51 | cmp r1, r0\r |
| 52 | beq _Read_cp15_reg\r |
| 53 | \r |
| 54 | _CPU_is_not_A15\r |
| 55 | mov r2, lr ; Save link register\r |
| 56 | bl ArmGetScuBaseAddress ; Read SCU Base Address\r |
| 57 | mov lr, r2 ; Restore link register val\r |
| 58 | ldr r0, [r0, #A9_SCU_CONFIG_OFFSET] ; Read SCU Config reg to get CPU count\r |
| 59 | b _Return\r |
| 60 | \r |
| 61 | _Read_cp15_reg\r |
| 62 | mrc p15, 1, r0, c9, c0, 2 ; Read C9 register of CP15 to get CPU count\r |
| 63 | lsr r0, #24\r |
| 64 | \r |
| 65 | \r |
| 66 | _Return\r |
| 67 | and r0, r0, #3\r |
| 68 | // Add '1' to the number of CPU on the Cluster\r |
| 69 | add r0, r0, #1\r |
| 70 | ldmfd SP!, {r1-r2}\r |
| 71 | bx lr\r |
| 72 | \r |
| 73 | END\r |
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