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f9849036 AB |
1 | #\r |
2 | # Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r | |
3 | #\r | |
4 | # This program and the accompanying materials\r | |
5 | # are licensed and made available under the terms and conditions of the BSD License\r | |
6 | # which accompanies this distribution. The full text of the license may be found at\r | |
7 | # http://opensource.org/licenses/bsd-license.php\r | |
8 | #\r | |
9 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
10 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
11 | #\r | |
12 | #\r | |
13 | \r | |
14 | #include <AsmMacroIoLibV8.h>\r | |
15 | #include <Base.h>\r | |
16 | #include <Library/ArmLib.h>\r | |
17 | #include <Library/PcdLib.h>\r | |
18 | #include <AutoGen.h>\r | |
19 | \r | |
20 | .text\r | |
21 | .align 2\r | |
22 | \r | |
23 | GCC_ASM_EXPORT(ArmPlatformPeiBootAction)\r | |
24 | GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)\r | |
25 | GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)\r | |
26 | GCC_ASM_EXPORT(ArmPlatformGetCorePosition)\r | |
27 | GCC_ASM_EXPORT(ArmGetPhysAddrTop)\r | |
28 | \r | |
29 | GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore)\r | |
30 | GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)\r | |
31 | GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdCoreCount)\r | |
32 | \r | |
33 | .LFdtMagic:\r | |
34 | .byte 0xd0, 0x0d, 0xfe, 0xed\r | |
35 | \r | |
36 | .LArm64LinuxMagic:\r | |
37 | .byte 0x41, 0x52, 0x4d, 0x64\r | |
38 | \r | |
39 | // VOID\r | |
40 | // ArmPlatformPeiBootAction (\r | |
41 | // VOID *DeviceTreeBaseAddress, // passed by loader in x0\r | |
42 | // VOID *ImageBase // passed by FDF trampoline in x1\r | |
43 | // );\r | |
44 | ASM_PFX(ArmPlatformPeiBootAction):\r | |
45 | mov x29, x30 // preserve LR\r | |
46 | \r | |
47 | //\r | |
48 | // If we are booting from RAM using the Linux kernel boot protocol, x0 will\r | |
49 | // point to the DTB image in memory. Otherwise, we are just coming out of\r | |
50 | // reset, and x0 will be 0. Check also the FDT magic.\r | |
51 | //\r | |
52 | cbz x0, .Lout\r | |
53 | ldr w8, .LFdtMagic\r | |
54 | ldr w9, [x0]\r | |
55 | cmp w8, w9\r | |
56 | bne .Lout\r | |
57 | \r | |
58 | //\r | |
59 | // The base of the runtime image has been preserved in x1. Check whether\r | |
60 | // the expected magic number can be found in the header.\r | |
61 | //\r | |
62 | ldr w8, .LArm64LinuxMagic\r | |
63 | ldr w9, [x1, #0x38]\r | |
64 | cmp w8, w9\r | |
65 | bne .Lout\r | |
66 | \r | |
67 | //\r | |
68 | //\r | |
69 | // OK, so far so good. We have confirmed that we likely have a DTB and are\r | |
70 | // booting via the arm64 Linux boot protocol. Update the base-of-image PCD\r | |
71 | // to the actual relocated value, and add the shift of PcdFdBaseAddress to\r | |
72 | // PcdFvBaseAddress as well\r | |
73 | //\r | |
74 | adr x8, PcdGet64 (PcdFdBaseAddress)\r | |
75 | adr x9, PcdGet64 (PcdFvBaseAddress)\r | |
76 | ldr x6, [x8]\r | |
77 | ldr x7, [x9]\r | |
78 | sub x7, x7, x6\r | |
79 | add x7, x7, x1\r | |
80 | str x1, [x8]\r | |
81 | str x7, [x9]\r | |
82 | \r | |
83 | //\r | |
84 | // Copy the DTB to the slack space right after the 64 byte arm64/Linux style\r | |
85 | // image header at the base of this image (defined in the FDF), and record the\r | |
86 | // pointer in PcdDeviceTreeInitialBaseAddress.\r | |
87 | //\r | |
88 | adr x8, PcdGet64 (PcdDeviceTreeInitialBaseAddress)\r | |
89 | add x1, x1, #0x40\r | |
90 | str x1, [x8]\r | |
91 | \r | |
92 | ldr w8, [x0, #4] // get DTB size (BE)\r | |
93 | mov x9, x1\r | |
94 | rev w8, w8\r | |
95 | add x8, x8, x0\r | |
96 | 0:ldp x6, x7, [x0], #16\r | |
97 | stp x6, x7, [x9], #16\r | |
98 | cmp x0, x8\r | |
99 | blt 0b\r | |
100 | \r | |
101 | //\r | |
102 | // Discover the memory size and offset from the DTB, and record in the\r | |
103 | // respective PCDs\r | |
104 | //\r | |
105 | mov x0, x1\r | |
106 | bl find_memnode // returns (size, base) size in (x0, x1)\r | |
107 | cbz x0, .Lout\r | |
108 | \r | |
109 | adr x8, PcdGet64 (PcdSystemMemorySize)\r | |
110 | adr x9, PcdGet64 (PcdSystemMemoryBase)\r | |
111 | str x0, [x8]\r | |
112 | str x1, [x9]\r | |
113 | \r | |
114 | .Lout:\r | |
115 | ret x29\r | |
116 | \r | |
117 | //UINTN\r | |
118 | //ArmPlatformGetPrimaryCoreMpId (\r | |
119 | // VOID\r | |
120 | // );\r | |
121 | ASM_PFX(ArmPlatformGetPrimaryCoreMpId):\r | |
122 | LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, x0)\r | |
123 | ldrh w0, [x0]\r | |
124 | ret\r | |
125 | \r | |
126 | //UINTN\r | |
127 | //ArmPlatformIsPrimaryCore (\r | |
128 | // IN UINTN MpId\r | |
129 | // );\r | |
130 | ASM_PFX(ArmPlatformIsPrimaryCore):\r | |
131 | mov x0, #1\r | |
132 | ret\r | |
133 | \r | |
134 | //UINTN\r | |
135 | //ArmPlatformGetCorePosition (\r | |
136 | // IN UINTN MpId\r | |
137 | // );\r | |
138 | // With this function: CorePos = (ClusterId * 4) + CoreId\r | |
139 | ASM_PFX(ArmPlatformGetCorePosition):\r | |
140 | and x1, x0, #ARM_CORE_MASK\r | |
141 | and x0, x0, #ARM_CLUSTER_MASK\r | |
142 | add x0, x1, x0, LSR #6\r | |
143 | ret\r | |
144 | \r | |
145 | //EFI_PHYSICAL_ADDRESS\r | |
146 | //GetPhysAddrTop (\r | |
147 | // VOID\r | |
148 | // );\r | |
149 | ASM_PFX(ArmGetPhysAddrTop):\r | |
150 | mrs x0, id_aa64mmfr0_el1\r | |
151 | adr x1, .LPARanges\r | |
152 | and x0, x0, #7\r | |
153 | ldrb w1, [x1, x0]\r | |
154 | mov x0, #1\r | |
155 | lsl x0, x0, x1\r | |
156 | ret\r | |
157 | \r | |
158 | //\r | |
159 | // Bits 0..2 of the AA64MFR0_EL1 system register encode the size of the\r | |
160 | // physical address space support on this CPU:\r | |
161 | // 0 == 32 bits, 1 == 36 bits, etc etc\r | |
162 | // 6 and 7 are reserved\r | |
163 | //\r | |
164 | .LPARanges:\r | |
165 | .byte 32, 36, 40, 42, 44, 48, -1, -1\r | |
166 | \r | |
167 | ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r |