ArmPlatformPkg/ArmVExpressSecLibRTSM: Only use extended name of system registers...
[mirror_edk2.git] / ArmPlatformPkg / Drivers / NorFlashDxe / NorFlashDxe.h
CommitLineData
1e57a462 1/** @file NorFlashDxe.h\r
2\r
2dff0c1a 3 Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>\r
1e57a462 4\r
5 This program and the accompanying materials\r
6 are licensed and made available under the terms and conditions of the BSD License\r
7 which accompanies this distribution. The full text of the license may be found at\r
8 http://opensource.org/licenses/bsd-license.php\r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13**/\r
14\r
15#ifndef __NOR_FLASH_DXE_H__\r
16#define __NOR_FLASH_DXE_H__\r
17\r
18\r
19#include <Base.h>\r
20#include <PiDxe.h>\r
21\r
1dbbfc17
OM
22#include <Guid/EventGroup.h>\r
23\r
1e57a462 24#include <Protocol/BlockIo.h>\r
25#include <Protocol/FirmwareVolumeBlock.h>\r
26\r
27#include <Library/DebugLib.h>\r
28#include <Library/IoLib.h>\r
29#include <Library/NorFlashPlatformLib.h>\r
30#include <Library/UefiLib.h>\r
2dff0c1a 31#include <Library/UefiRuntimeLib.h>\r
1e57a462 32\r
33#define NOR_FLASH_ERASE_RETRY 10\r
34\r
35// Device access macros\r
36// These are necessary because we use 2 x 16bit parts to make up 32bit data\r
37\r
38#define HIGH_16_BITS 0xFFFF0000\r
39#define LOW_16_BITS 0x0000FFFF\r
40#define LOW_8_BITS 0x000000FF\r
41\r
42#define FOLD_32BIT_INTO_16BIT(value) ( ( value >> 16 ) | ( value & LOW_16_BITS ) )\r
43\r
44#define GET_LOW_BYTE(value) ( value & LOW_8_BITS )\r
45#define GET_HIGH_BYTE(value) ( GET_LOW_BYTE( value >> 16 ) )\r
46\r
47// Each command must be sent simultaneously to both chips,\r
48// i.e. at the lower 16 bits AND at the higher 16 bits\r
49#define CREATE_NOR_ADDRESS(BaseAddr,OffsetAddr) ((BaseAddr) + ((OffsetAddr) << 2))\r
50#define CREATE_DUAL_CMD(Cmd) ( ( Cmd << 16) | ( Cmd & LOW_16_BITS) )\r
51#define SEND_NOR_COMMAND(BaseAddr,Offset,Cmd) MmioWrite32 (CREATE_NOR_ADDRESS(BaseAddr,Offset), CREATE_DUAL_CMD(Cmd))\r
52#define GET_NOR_BLOCK_ADDRESS(BaseAddr,Lba,LbaSize)( BaseAddr + (UINTN)((Lba) * LbaSize) )\r
53\r
54// Status Register Bits\r
55#define P30_SR_BIT_WRITE (BIT7 << 16 | BIT7)\r
56#define P30_SR_BIT_ERASE_SUSPEND (BIT6 << 16 | BIT6)\r
57#define P30_SR_BIT_ERASE (BIT5 << 16 | BIT5)\r
58#define P30_SR_BIT_PROGRAM (BIT4 << 16 | BIT4)\r
59#define P30_SR_BIT_VPP (BIT3 << 16 | BIT3)\r
60#define P30_SR_BIT_PROGRAM_SUSPEND (BIT2 << 16 | BIT2)\r
61#define P30_SR_BIT_BLOCK_LOCKED (BIT1 << 16 | BIT1)\r
62#define P30_SR_BIT_BEFP (BIT0 << 16 | BIT0)\r
63\r
64// Device Commands for Intel StrataFlash(R) Embedded Memory (P30) Family\r
65\r
66// On chip buffer size for buffered programming operations\r
67// There are 2 chips, each chip can buffer up to 32 (16-bit)words, and each word is 2 bytes.\r
68// Therefore the total size of the buffer is 2 x 32 x 2 = 128 bytes\r
69#define P30_MAX_BUFFER_SIZE_IN_BYTES ((UINTN)128)\r
70#define P30_MAX_BUFFER_SIZE_IN_WORDS (P30_MAX_BUFFER_SIZE_IN_BYTES/((UINTN)4))\r
71#define MAX_BUFFERED_PROG_ITERATIONS 10000000\r
72#define BOUNDARY_OF_32_WORDS 0x7F\r
73\r
74// CFI Addresses\r
75#define P30_CFI_ADDR_QUERY_UNIQUE_QRY 0x10\r
76#define P30_CFI_ADDR_VENDOR_ID 0x13\r
77\r
78// CFI Data\r
79#define CFI_QRY 0x00595251\r
80\r
81// READ Commands\r
82#define P30_CMD_READ_DEVICE_ID 0x0090\r
83#define P30_CMD_READ_STATUS_REGISTER 0x0070\r
84#define P30_CMD_CLEAR_STATUS_REGISTER 0x0050\r
85#define P30_CMD_READ_ARRAY 0x00FF\r
86#define P30_CMD_READ_CFI_QUERY 0x0098\r
87\r
88// WRITE Commands\r
89#define P30_CMD_WORD_PROGRAM_SETUP 0x0040\r
90#define P30_CMD_ALTERNATE_WORD_PROGRAM_SETUP 0x0010\r
91#define P30_CMD_BUFFERED_PROGRAM_SETUP 0x00E8\r
92#define P30_CMD_BUFFERED_PROGRAM_CONFIRM 0x00D0\r
93#define P30_CMD_BEFP_SETUP 0x0080\r
94#define P30_CMD_BEFP_CONFIRM 0x00D0\r
95\r
96// ERASE Commands\r
97#define P30_CMD_BLOCK_ERASE_SETUP 0x0020\r
98#define P30_CMD_BLOCK_ERASE_CONFIRM 0x00D0\r
99\r
100// SUSPEND Commands\r
101#define P30_CMD_PROGRAM_OR_ERASE_SUSPEND 0x00B0\r
102#define P30_CMD_SUSPEND_RESUME 0x00D0\r
103\r
104// BLOCK LOCKING / UNLOCKING Commands\r
105#define P30_CMD_LOCK_BLOCK_SETUP 0x0060\r
106#define P30_CMD_LOCK_BLOCK 0x0001\r
107#define P30_CMD_UNLOCK_BLOCK 0x00D0\r
108#define P30_CMD_LOCK_DOWN_BLOCK 0x002F\r
109\r
110// PROTECTION Commands\r
111#define P30_CMD_PROGRAM_PROTECTION_REGISTER_SETUP 0x00C0\r
112\r
113// CONFIGURATION Commands\r
114#define P30_CMD_READ_CONFIGURATION_REGISTER_SETUP 0x0060\r
115#define P30_CMD_READ_CONFIGURATION_REGISTER 0x0003\r
116\r
117#define NOR_FLASH_SIGNATURE SIGNATURE_32('n', 'o', 'r', '0')\r
118#define INSTANCE_FROM_FVB_THIS(a) CR(a, NOR_FLASH_INSTANCE, FvbProtocol, NOR_FLASH_SIGNATURE)\r
119#define INSTANCE_FROM_BLKIO_THIS(a) CR(a, NOR_FLASH_INSTANCE, BlockIoProtocol, NOR_FLASH_SIGNATURE)\r
120\r
121typedef struct _NOR_FLASH_INSTANCE NOR_FLASH_INSTANCE;\r
122\r
123typedef EFI_STATUS (*NOR_FLASH_INITIALIZE) (NOR_FLASH_INSTANCE* Instance);\r
124\r
125typedef struct {\r
126 VENDOR_DEVICE_PATH Vendor;\r
127 EFI_DEVICE_PATH_PROTOCOL End;\r
128} NOR_FLASH_DEVICE_PATH;\r
129\r
130struct _NOR_FLASH_INSTANCE {\r
131 UINT32 Signature;\r
132 EFI_HANDLE Handle;\r
133\r
134 BOOLEAN Initialized;\r
135 NOR_FLASH_INITIALIZE Initialize;\r
136\r
137 UINTN DeviceBaseAddress;\r
138 UINTN RegionBaseAddress;\r
139 UINTN Size;\r
140 EFI_LBA StartLba;\r
141\r
142 EFI_BLOCK_IO_PROTOCOL BlockIoProtocol;\r
143 EFI_BLOCK_IO_MEDIA Media;\r
144\r
145 BOOLEAN SupportFvb;\r
146 EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL FvbProtocol;\r
2dff0c1a 147 VOID* FvbBuffer;\r
1e57a462 148\r
149 NOR_FLASH_DEVICE_PATH DevicePath;\r
150};\r
151\r
152EFI_STATUS\r
153NorFlashReadCfiData (\r
154 IN UINTN DeviceBaseAddress,\r
155 IN UINTN CFI_Offset,\r
156 IN UINT32 NumberOfBytes,\r
157 OUT UINT32 *Data\r
158 );\r
159\r
160EFI_STATUS\r
161NorFlashWriteBuffer (\r
162 IN NOR_FLASH_INSTANCE *Instance,\r
163 IN UINTN TargetAddress,\r
164 IN UINTN BufferSizeInBytes,\r
165 IN UINT32 *Buffer\r
166 );\r
167\r
168//\r
169// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.Reset\r
170//\r
171EFI_STATUS\r
172EFIAPI\r
173NorFlashBlockIoReset (\r
174 IN EFI_BLOCK_IO_PROTOCOL *This,\r
175 IN BOOLEAN ExtendedVerification\r
176 );\r
177\r
178//\r
179// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.ReadBlocks\r
180//\r
181EFI_STATUS\r
182EFIAPI\r
183NorFlashBlockIoReadBlocks (\r
184 IN EFI_BLOCK_IO_PROTOCOL *This,\r
185 IN UINT32 MediaId,\r
186 IN EFI_LBA Lba,\r
187 IN UINTN BufferSizeInBytes,\r
188 OUT VOID *Buffer\r
189);\r
190\r
191//\r
192// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.WriteBlocks\r
193//\r
194EFI_STATUS\r
195EFIAPI\r
196NorFlashBlockIoWriteBlocks (\r
197 IN EFI_BLOCK_IO_PROTOCOL *This,\r
198 IN UINT32 MediaId,\r
199 IN EFI_LBA Lba,\r
200 IN UINTN BufferSizeInBytes,\r
201 IN VOID *Buffer\r
202);\r
203\r
204//\r
205// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.FlushBlocks\r
206//\r
207EFI_STATUS\r
208EFIAPI\r
209NorFlashBlockIoFlushBlocks (\r
210 IN EFI_BLOCK_IO_PROTOCOL *This\r
211);\r
212\r
213\r
214//\r
215// NorFlashFvbDxe.c\r
216//\r
217\r
218EFI_STATUS\r
219EFIAPI\r
220NorFlashFvbInitialize (\r
221 IN NOR_FLASH_INSTANCE* Instance\r
222 );\r
223\r
224EFI_STATUS\r
225EFIAPI\r
226FvbGetAttributes(\r
227 IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,\r
228 OUT EFI_FVB_ATTRIBUTES_2 *Attributes\r
229 );\r
230\r
231EFI_STATUS\r
232EFIAPI\r
233FvbSetAttributes(\r
234 IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,\r
235 IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes\r
236 );\r
237\r
238EFI_STATUS\r
239EFIAPI\r
240FvbGetPhysicalAddress(\r
241 IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,\r
242 OUT EFI_PHYSICAL_ADDRESS *Address\r
243 );\r
244\r
245EFI_STATUS\r
246EFIAPI\r
247FvbGetBlockSize(\r
248 IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,\r
249 IN EFI_LBA Lba,\r
250 OUT UINTN *BlockSize,\r
251 OUT UINTN *NumberOfBlocks\r
252 );\r
253\r
254EFI_STATUS\r
255EFIAPI\r
256FvbRead(\r
257 IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,\r
258 IN EFI_LBA Lba,\r
259 IN UINTN Offset,\r
260 IN OUT UINTN *NumBytes,\r
261 IN OUT UINT8 *Buffer\r
262 );\r
263\r
264EFI_STATUS\r
265EFIAPI\r
266FvbWrite(\r
267 IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,\r
268 IN EFI_LBA Lba,\r
269 IN UINTN Offset,\r
270 IN OUT UINTN *NumBytes,\r
271 IN UINT8 *Buffer\r
272 );\r
273\r
274EFI_STATUS\r
275EFIAPI\r
276FvbEraseBlocks(\r
277 IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,\r
278 ...\r
279 );\r
280\r
281//\r
282// NorFlashDxe.c\r
283//\r
284\r
285EFI_STATUS\r
286NorFlashUnlockAndEraseSingleBlock (\r
287 IN NOR_FLASH_INSTANCE *Instance,\r
288 IN UINTN BlockAddress\r
289 );\r
290\r
291EFI_STATUS\r
292NorFlashWriteSingleBlock (\r
293 IN NOR_FLASH_INSTANCE *Instance,\r
294 IN EFI_LBA Lba,\r
295 IN UINT32 *DataBuffer,\r
296 IN UINT32 BlockSizeInWords\r
297 );\r
298\r
299EFI_STATUS\r
300NorFlashWriteBlocks (\r
301 IN NOR_FLASH_INSTANCE *Instance,\r
302 IN EFI_LBA Lba,\r
303 IN UINTN BufferSizeInBytes,\r
304 IN VOID *Buffer\r
305 );\r
306\r
518c243d
HL
307EFI_STATUS\r
308NorFlashWriteSingleWord (\r
309 IN NOR_FLASH_INSTANCE *Instance,\r
310 IN UINTN WordAddress,\r
311 IN UINT32 WriteData\r
312 );\r
313\r
1e57a462 314EFI_STATUS\r
315NorFlashReadBlocks (\r
316 IN NOR_FLASH_INSTANCE *Instance,\r
317 IN EFI_LBA Lba,\r
318 IN UINTN BufferSizeInBytes,\r
319 OUT VOID *Buffer\r
320 );\r
321\r
518c243d
HL
322EFI_STATUS\r
323NorFlashRead (\r
324 IN NOR_FLASH_INSTANCE *Instance,\r
325 IN EFI_LBA Lba,\r
326 IN UINTN Offset,\r
327 IN UINTN BufferSizeInBytes,\r
328 OUT VOID *Buffer\r
329 );\r
330\r
1e57a462 331EFI_STATUS\r
332NorFlashReset (\r
333 IN NOR_FLASH_INSTANCE *Instance\r
334 );\r
335\r
518c243d
HL
336EFI_STATUS\r
337NorFlashUnlockSingleBlockIfNecessary (\r
338 IN NOR_FLASH_INSTANCE *Instance,\r
339 IN UINTN BlockAddress\r
340 );\r
341\r
1e57a462 342#endif /* __NOR_FLASH_DXE_H__ */\r