projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 33e7c2ab | 1 | /** @file\r |
| 5a5440d0 PG |
2 | \r |
| 3 | Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r | |
| 4 | \r | |
| 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
| 6 | \r | |
| 33e7c2ab | 7 | **/\r |
| 8 | \r | |
| 9 | \r | |
| 10 | #ifndef __SP805_WATCHDOG_H__\r | |
| 11 | #define __SP805_WATCHDOG_H__\r | |
| 12 | \r | |
| 33e7c2ab | 13 | // SP805 Watchdog Registers\r |
| 5cc45b70 | 14 | #define SP805_WDOG_LOAD_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x000)\r |
| 15 | #define SP805_WDOG_CURRENT_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x004)\r | |
| 16 | #define SP805_WDOG_CONTROL_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x008)\r | |
| 17 | #define SP805_WDOG_INT_CLR_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x00C)\r | |
| 18 | #define SP805_WDOG_RAW_INT_STS_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x010)\r | |
| 19 | #define SP805_WDOG_MSK_INT_STS_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x014)\r | |
| 20 | #define SP805_WDOG_LOCK_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xC00)\r | |
| 33e7c2ab | 21 | \r |
| 5cc45b70 | 22 | #define SP805_WDOG_PERIPH_ID0 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFE0)\r |
| 23 | #define SP805_WDOG_PERIPH_ID1 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFE4)\r | |
| 24 | #define SP805_WDOG_PERIPH_ID2 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFE8)\r | |
| 25 | #define SP805_WDOG_PERIPH_ID3 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFEC)\r | |
| 33e7c2ab | 26 | \r |
| 5cc45b70 | 27 | #define SP805_WDOG_PCELL_ID0 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFF0)\r |
| 28 | #define SP805_WDOG_PCELL_ID1 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFF4)\r | |
| 29 | #define SP805_WDOG_PCELL_ID2 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFF8)\r | |
| 30 | #define SP805_WDOG_PCELL_ID3 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFFC)\r | |
| 33e7c2ab | 31 | \r |
| 32 | // Timer control register bit definitions\r | |
| 33 | #define SP805_WDOG_CTRL_INTEN BIT0\r | |
| 34 | #define SP805_WDOG_CTRL_RESEN BIT1\r | |
| 35 | #define SP805_WDOG_RAW_INT_STS_WDOGRIS BIT0\r | |
| 36 | #define SP805_WDOG_MSK_INT_STS_WDOGMIS BIT0\r | |
| 37 | \r | |
| 38 | #define SP805_WDOG_LOCK_IS_UNLOCKED 0x00000000\r | |
| 39 | #define SP805_WDOG_LOCK_IS_LOCKED 0x00000001\r | |
| 40 | #define SP805_WDOG_SPECIAL_UNLOCK_CODE 0x1ACCE551\r | |
| 41 | \r | |
| 33e7c2ab | 42 | #endif // __SP805_WATCHDOG_H__\r |