[mirror_edk2.git] / ArmPlatformPkg / Include / Drivers / PL011Uart.h

/** @file\r
*\r
*  Copyright (c) 2011-2016, ARM Limited. All rights reserved.\r
*\r
*  This program and the accompanying materials\r
*  are licensed and made available under the terms and conditions of the BSD License\r
*  which accompanies this distribution.  The full text of the license may be found at\r
*  http://opensource.org/licenses/bsd-license.php\r
*\r
*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
*\r
**/\r
\r
#ifndef __PL011_UART_H__\r
#define __PL011_UART_H__\r
\r
#include <Uefi.h>\r
#include <Protocol/SerialIo.h>\r
\r
// PL011 Registers\r
#define UARTDR                    0x000\r
#define UARTRSR                   0x004\r
#define UARTECR                   0x004\r
#define UARTFR                    0x018\r
#define UARTILPR                  0x020\r
#define UARTIBRD                  0x024\r
#define UARTFBRD                  0x028\r
#define UARTLCR_H                 0x02C\r
#define UARTCR                    0x030\r
#define UARTIFLS                  0x034\r
#define UARTIMSC                  0x038\r
#define UARTRIS                   0x03C\r
#define UARTMIS                   0x040\r
#define UARTICR                   0x044\r
#define UARTDMACR                 0x048\r
\r
#define UARTPID0                  0xFE0\r
#define UARTPID1                  0xFE4\r
#define UARTPID2                  0xFE8\r
#define UARTPID3                  0xFEC\r
\r
// Data status bits\r
#define UART_DATA_ERROR_MASK      0x0F00\r
\r
// Status reg bits\r
#define UART_STATUS_ERROR_MASK    0x0F\r
\r
// Flag reg bits\r
#define PL011_UARTFR_RI           (1 << 8)  // Ring indicator\r
#define PL011_UARTFR_TXFE         (1 << 7)  // Transmit FIFO empty\r
#define PL011_UARTFR_RXFF         (1 << 6)  // Receive  FIFO full\r
#define PL011_UARTFR_TXFF         (1 << 5)  // Transmit FIFO full\r
#define PL011_UARTFR_RXFE         (1 << 4)  // Receive  FIFO empty\r
#define PL011_UARTFR_BUSY         (1 << 3)  // UART busy\r
#define PL011_UARTFR_DCD          (1 << 2)  // Data carrier detect\r
#define PL011_UARTFR_DSR          (1 << 1)  // Data set ready\r
#define PL011_UARTFR_CTS          (1 << 0)  // Clear to send\r
\r
// Flag reg bits - alternative names\r
#define UART_TX_EMPTY_FLAG_MASK   PL011_UARTFR_TXFE\r
#define UART_RX_FULL_FLAG_MASK    PL011_UARTFR_RXFF\r
#define UART_TX_FULL_FLAG_MASK    PL011_UARTFR_TXFF\r
#define UART_RX_EMPTY_FLAG_MASK   PL011_UARTFR_RXFE\r
#define UART_BUSY_FLAG_MASK       PL011_UARTFR_BUSY\r
\r
// Control reg bits\r
#define PL011_UARTCR_CTSEN        (1 << 15) // CTS hardware flow control enable\r
#define PL011_UARTCR_RTSEN        (1 << 14) // RTS hardware flow control enable\r
#define PL011_UARTCR_RTS          (1 << 11) // Request to send\r
#define PL011_UARTCR_DTR          (1 << 10) // Data transmit ready.\r
#define PL011_UARTCR_RXE          (1 << 9)  // Receive enable\r
#define PL011_UARTCR_TXE          (1 << 8)  // Transmit enable\r
#define PL011_UARTCR_LBE          (1 << 7)  // Loopback enable\r
#define PL011_UARTCR_UARTEN       (1 << 0)  // UART Enable\r
\r
// Line Control Register Bits\r
#define PL011_UARTLCR_H_SPS       (1 << 7)  // Stick parity select\r
#define PL011_UARTLCR_H_WLEN_8    (3 << 5)\r
#define PL011_UARTLCR_H_WLEN_7    (2 << 5)\r
#define PL011_UARTLCR_H_WLEN_6    (1 << 5)\r
#define PL011_UARTLCR_H_WLEN_5    (0 << 5)\r
#define PL011_UARTLCR_H_FEN       (1 << 4)  // FIFOs Enable\r
#define PL011_UARTLCR_H_STP2      (1 << 3)  // Two stop bits select\r
#define PL011_UARTLCR_H_EPS       (1 << 2)  // Even parity select\r
#define PL011_UARTLCR_H_PEN       (1 << 1)  // Parity Enable\r
#define PL011_UARTLCR_H_BRK       (1 << 0)  // Send break\r
\r
#define PL011_UARTPID2_VER(X)     (((X) >> 4) & 0xF)\r
#define PL011_VER_R1P4            0x2\r
\r
/**\r
\r
  Initialise the serial port to the specified settings.\r
  All unspecified settings will be set to the default values.\r
\r
  @param[in]  UartBase            The base address of the serial device.\r
  @param[in]  UartClkInHz         The clock in Hz for the serial device.\r
                                  Ignored if the PCD PL011UartInteger is not 0\r
  @param[in out] BaudRate         The baud rate of the serial device. If the\r
                                  baud rate is not supported, the speed will be\r
                                  reduced to the nearest supported one and the\r
                                  variable's value will be updated accordingly.\r
  @param[in out] ReceiveFifoDepth The number of characters the device will\r
                                  buffer on input.  Value of 0 will use the\r
                                  device's default FIFO depth.\r
  @param[in out]  Parity          If applicable, this is the EFI_PARITY_TYPE\r
                                  that is computed or checked as each character\r
                                  is transmitted or received. If the device\r
                                  does not support parity, the value is the\r
                                  default parity value.\r
  @param[in out]  DataBits        The number of data bits in each character.\r
  @param[in out]  StopBits        If applicable, the EFI_STOP_BITS_TYPE number\r
                                  of stop bits per character.\r
                                  If the device does not support stop bits, the\r
                                  value is the default stop bit value.\r
\r
  @retval RETURN_SUCCESS            All attributes were set correctly on the\r
                                    serial device.\r
  @retval RETURN_INVALID_PARAMETER  One or more of the attributes has an\r
                                    unsupported value.\r
\r
**/\r
RETURN_STATUS\r
EFIAPI\r
PL011UartInitializePort (\r
  IN     UINTN               UartBase,\r
  IN     UINT32              UartClkInHz,\r
  IN OUT UINT64              *BaudRate,\r
  IN OUT UINT32              *ReceiveFifoDepth,\r
  IN OUT EFI_PARITY_TYPE     *Parity,\r
  IN OUT UINT8               *DataBits,\r
  IN OUT EFI_STOP_BITS_TYPE  *StopBits\r
  );\r
\r
/**\r
\r
  Assert or deassert the control signals on a serial port.\r
  The following control signals are set according their bit settings :\r
  . Request to Send\r
  . Data Terminal Ready\r
\r
  @param[in]  UartBase  UART registers base address\r
  @param[in]  Control   The following bits are taken into account :\r
                        . EFI_SERIAL_REQUEST_TO_SEND : assert/deassert the\r
                          "Request To Send" control signal if this bit is\r
                          equal to one/zero.\r
                        . EFI_SERIAL_DATA_TERMINAL_READY : assert/deassert\r
                          the "Data Terminal Ready" control signal if this\r
                          bit is equal to one/zero.\r
                        . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/disable\r
                          the hardware loopback if this bit is equal to\r
                          one/zero.\r
                        . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supported.\r
                        . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enable/\r
                          disable the hardware flow control based on CTS (Clear\r
                          To Send) and RTS (Ready To Send) control signals.\r
\r
  @retval  RETURN_SUCCESS      The new control bits were set on the device.\r
  @retval  RETURN_UNSUPPORTED  The device does not support this operation.\r
\r
**/\r
RETURN_STATUS\r
EFIAPI\r
PL011UartSetControl (\r
  IN UINTN   UartBase,\r
  IN UINT32  Control\r
  );\r
\r
/**\r
\r
  Retrieve the status of the control bits on a serial device.\r
\r
  @param[in]   UartBase  UART registers base address\r
  @param[out]  Control   Status of the control bits on a serial device :\r
\r
                         . EFI_SERIAL_DATA_CLEAR_TO_SEND,\r
                           EFI_SERIAL_DATA_SET_READY,\r
                           EFI_SERIAL_RING_INDICATE,\r
                           EFI_SERIAL_CARRIER_DETECT,\r
                           EFI_SERIAL_REQUEST_TO_SEND,\r
                           EFI_SERIAL_DATA_TERMINAL_READY\r
                           are all related to the DTE (Data Terminal Equipment)\r
                           and DCE (Data Communication Equipment) modes of\r
                           operation of the serial device.\r
                         . EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the\r
                           receive buffer is empty, 0 otherwise.\r
                         . EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the\r
                           transmit buffer is empty, 0 otherwise.\r
                         . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if\r
                           the hardware loopback is enabled (the ouput feeds the\r
                           receive buffer), 0 otherwise.\r
                         . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one if\r
                           a loopback is accomplished by software, 0 otherwise.\r
                         . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to\r
                           one if the hardware flow control based on CTS (Clear\r
                           To Send) and RTS (Ready To Send) control signals is\r
                           enabled, 0 otherwise.\r
\r
  @retval RETURN_SUCCESS  The control bits were read from the serial device.\r
\r
**/\r
RETURN_STATUS\r
EFIAPI\r
PL011UartGetControl (\r
  IN UINTN     UartBase,\r
  OUT UINT32  *Control\r
  );\r
\r
/**\r
  Write data to serial device.\r
\r
  @param  Buffer           Point of data buffer which need to be written.\r
  @param  NumberOfBytes    Number of output bytes which are cached in Buffer.\r
\r
  @retval 0                Write data failed.\r
  @retval !0               Actual number of bytes written to serial device.\r
\r
**/\r
UINTN\r
EFIAPI\r
PL011UartWrite (\r
  IN  UINTN       UartBase,\r
  IN  UINT8       *Buffer,\r
  IN  UINTN       NumberOfBytes\r
  );\r
\r
/**\r
  Read data from serial device and save the data in buffer.\r
\r
  @param  Buffer           Point of data buffer which need to be written.\r
  @param  NumberOfBytes    Number of output bytes which are cached in Buffer.\r
\r
  @retval 0                Read data failed.\r
  @retval !0               Actual number of bytes read from serial device.\r
\r
**/\r
UINTN\r
EFIAPI\r
PL011UartRead (\r
  IN  UINTN       UartBase,\r
  OUT UINT8       *Buffer,\r
  IN  UINTN       NumberOfBytes\r
  );\r
\r
/**\r
  Check to see if any data is available to be read from the debug device.\r
\r
  @retval TRUE       At least one byte of data is available to be read\r
  @retval FALSE      No data is available to be read\r
\r
**/\r
BOOLEAN\r
EFIAPI\r
PL011UartPoll (\r
  IN  UINTN       UartBase\r
  );\r
\r
#endif\r
Commit	Line	Data
051e63bb	1	/** @file\r
051e63bb	2	*\r
9f08a052	3	* Copyright (c) 2011-2016, ARM Limited. All rights reserved.\r
051e63bb	4	*\r
3402aac7 RC	5	* This program and the accompanying materials\r
	6	* are licensed and made available under the terms and conditions of the BSD License\r
	7	* which accompanies this distribution. The full text of the license may be found at\r
	8	* http://opensource.org/licenses/bsd-license.php\r
	9	*\r
	10	* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
051e63bb	12	*\r
	13	**/\r
	14	\r
	15	#ifndef __PL011_UART_H__\r
	16	#define __PL011_UART_H__\r
	17	\r
	18	#include <Uefi.h>\r
	19	#include <Protocol/SerialIo.h>\r
	20	\r
	21	// PL011 Registers\r
	22	#define UARTDR 0x000\r
	23	#define UARTRSR 0x004\r
	24	#define UARTECR 0x004\r
	25	#define UARTFR 0x018\r
	26	#define UARTILPR 0x020\r
	27	#define UARTIBRD 0x024\r
	28	#define UARTFBRD 0x028\r
	29	#define UARTLCR_H 0x02C\r
	30	#define UARTCR 0x030\r
	31	#define UARTIFLS 0x034\r
	32	#define UARTIMSC 0x038\r
	33	#define UARTRIS 0x03C\r
	34	#define UARTMIS 0x040\r
	35	#define UARTICR 0x044\r
	36	#define UARTDMACR 0x048\r
	37	\r
48edf6be LL	38	#define UARTPID0 0xFE0\r
	39	#define UARTPID1 0xFE4\r
	40	#define UARTPID2 0xFE8\r
	41	#define UARTPID3 0xFEC\r
	42	\r
051e63bb	43	// Data status bits\r
	44	#define UART_DATA_ERROR_MASK 0x0F00\r
	45	\r
	46	// Status reg bits\r
	47	#define UART_STATUS_ERROR_MASK 0x0F\r
	48	\r
	49	// Flag reg bits\r
	50	#define PL011_UARTFR_RI (1 << 8) // Ring indicator\r
	51	#define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty\r
	52	#define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full\r
	53	#define PL011_UARTFR_TXFF (1 << 5) // Transmit FIFO full\r
	54	#define PL011_UARTFR_RXFE (1 << 4) // Receive FIFO empty\r
	55	#define PL011_UARTFR_BUSY (1 << 3) // UART busy\r
	56	#define PL011_UARTFR_DCD (1 << 2) // Data carrier detect\r
	57	#define PL011_UARTFR_DSR (1 << 1) // Data set ready\r
	58	#define PL011_UARTFR_CTS (1 << 0) // Clear to send\r
	59	\r
	60	// Flag reg bits - alternative names\r
	61	#define UART_TX_EMPTY_FLAG_MASK PL011_UARTFR_TXFE\r
	62	#define UART_RX_FULL_FLAG_MASK PL011_UARTFR_RXFF\r
	63	#define UART_TX_FULL_FLAG_MASK PL011_UARTFR_TXFF\r
	64	#define UART_RX_EMPTY_FLAG_MASK PL011_UARTFR_RXFE\r
	65	#define UART_BUSY_FLAG_MASK PL011_UARTFR_BUSY\r
	66	\r
	67	// Control reg bits\r
	68	#define PL011_UARTCR_CTSEN (1 << 15) // CTS hardware flow control enable\r
	69	#define PL011_UARTCR_RTSEN (1 << 14) // RTS hardware flow control enable\r
	70	#define PL011_UARTCR_RTS (1 << 11) // Request to send\r
	71	#define PL011_UARTCR_DTR (1 << 10) // Data transmit ready.\r
	72	#define PL011_UARTCR_RXE (1 << 9) // Receive enable\r
	73	#define PL011_UARTCR_TXE (1 << 8) // Transmit enable\r
	74	#define PL011_UARTCR_LBE (1 << 7) // Loopback enable\r
	75	#define PL011_UARTCR_UARTEN (1 << 0) // UART Enable\r
	76	\r
	77	// Line Control Register Bits\r
	78	#define PL011_UARTLCR_H_SPS (1 << 7) // Stick parity select\r
	79	#define PL011_UARTLCR_H_WLEN_8 (3 << 5)\r
	80	#define PL011_UARTLCR_H_WLEN_7 (2 << 5)\r
	81	#define PL011_UARTLCR_H_WLEN_6 (1 << 5)\r
	82	#define PL011_UARTLCR_H_WLEN_5 (0 << 5)\r
	83	#define PL011_UARTLCR_H_FEN (1 << 4) // FIFOs Enable\r
	84	#define PL011_UARTLCR_H_STP2 (1 << 3) // Two stop bits select\r
	85	#define PL011_UARTLCR_H_EPS (1 << 2) // Even parity select\r
	86	#define PL011_UARTLCR_H_PEN (1 << 1) // Parity Enable\r
	87	#define PL011_UARTLCR_H_BRK (1 << 0) // Send break\r
	88	\r
48edf6be LL	89	#define PL011_UARTPID2_VER(X) (((X) >> 4) & 0xF)\r
	90	#define PL011_VER_R1P4 0x2\r
	91	\r
f6300528	92	/**\r
051e63bb	93	\r
9f08a052 EL	94	Initialise the serial port to the specified settings.\r
	95	All unspecified settings will be set to the default values.\r
	96	\r
f6300528 EL	97	@param[in] UartBase The base address of the serial device.\r
	98	@param[in] UartClkInHz The clock in Hz for the serial device.\r
	99	Ignored if the PCD PL011UartInteger is not 0\r
	100	@param[in out] BaudRate The baud rate of the serial device. If the\r
9f08a052 EL	101	baud rate is not supported, the speed will be\r
	102	reduced to the nearest supported one and the\r
	103	variable's value will be updated accordingly.\r
f6300528	104	@param[in out] ReceiveFifoDepth The number of characters the device will\r
9f08a052 EL	105	buffer on input. Value of 0 will use the\r
9f08a052 EL	106	device's default FIFO depth.\r
f6300528	107	@param[in out] Parity If applicable, this is the EFI_PARITY_TYPE\r
9f08a052 EL	108	that is computed or checked as each character\r
	109	is transmitted or received. If the device\r
	110	does not support parity, the value is the\r
	111	default parity value.\r
f6300528 EL	112	@param[in out] DataBits The number of data bits in each character.\r
f6300528 EL	113	@param[in out] StopBits If applicable, the EFI_STOP_BITS_TYPE number\r
9f08a052 EL	114	of stop bits per character.\r
	115	If the device does not support stop bits, the\r
	116	value is the default stop bit value.\r
	117	\r
	118	@retval RETURN_SUCCESS All attributes were set correctly on the\r
	119	serial device.\r
	120	@retval RETURN_INVALID_PARAMETER One or more of the attributes has an\r
	121	unsupported value.\r
051e63bb	122	\r
	123	**/\r
	124	RETURN_STATUS\r
	125	EFIAPI\r
	126	PL011UartInitializePort (\r
9f08a052	127	IN UINTN UartBase,\r
f6300528	128	IN UINT32 UartClkInHz,\r
15e277d5	129	IN OUT UINT64 *BaudRate,\r
	130	IN OUT UINT32 *ReceiveFifoDepth,\r
	131	IN OUT EFI_PARITY_TYPE *Parity,\r
	132	IN OUT UINT8 *DataBits,\r
	133	IN OUT EFI_STOP_BITS_TYPE *StopBits\r
051e63bb	134	);\r
	135	\r
	136	/**\r
051e63bb	137	\r
ab716191 RC	138	Assert or deassert the control signals on a serial port.\r
	139	The following control signals are set according their bit settings :\r
	140	. Request to Send\r
	141	. Data Terminal Ready\r
	142	\r
	143	@param[in] UartBase UART registers base address\r
	144	@param[in] Control The following bits are taken into account :\r
	145	. EFI_SERIAL_REQUEST_TO_SEND : assert/deassert the\r
	146	"Request To Send" control signal if this bit is\r
	147	equal to one/zero.\r
	148	. EFI_SERIAL_DATA_TERMINAL_READY : assert/deassert\r
	149	the "Data Terminal Ready" control signal if this\r
	150	bit is equal to one/zero.\r
	151	. EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/disable\r
	152	the hardware loopback if this bit is equal to\r
	153	one/zero.\r
	154	. EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supported.\r
	155	. EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enable/\r
	156	disable the hardware flow control based on CTS (Clear\r
	157	To Send) and RTS (Ready To Send) control signals.\r
	158	\r
9f08a052 EL	159	@retval RETURN_SUCCESS The new control bits were set on the device.\r
9f08a052 EL	160	@retval RETURN_UNSUPPORTED The device does not support this operation.\r
051e63bb	161	\r
	162	**/\r
	163	RETURN_STATUS\r
	164	EFIAPI\r
	165	PL011UartSetControl (\r
ab716191 RC	166	IN UINTN UartBase,\r
ab716191 RC	167	IN UINT32 Control\r
051e63bb	168	);\r
	169	\r
	170	/**\r
051e63bb	171	\r
d2e7e385 RC	172	Retrieve the status of the control bits on a serial device.\r
	173	\r
	174	@param[in] UartBase UART registers base address\r
	175	@param[out] Control Status of the control bits on a serial device :\r
	176	\r
9f08a052 EL	177	. EFI_SERIAL_DATA_CLEAR_TO_SEND,\r
	178	EFI_SERIAL_DATA_SET_READY,\r
	179	EFI_SERIAL_RING_INDICATE,\r
	180	EFI_SERIAL_CARRIER_DETECT,\r
	181	EFI_SERIAL_REQUEST_TO_SEND,\r
	182	EFI_SERIAL_DATA_TERMINAL_READY\r
	183	are all related to the DTE (Data Terminal Equipment)\r
	184	and DCE (Data Communication Equipment) modes of\r
	185	operation of the serial device.\r
	186	. EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the\r
	187	receive buffer is empty, 0 otherwise.\r
	188	. EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the\r
	189	transmit buffer is empty, 0 otherwise.\r
	190	. EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if\r
	191	the hardware loopback is enabled (the ouput feeds the\r
	192	receive buffer), 0 otherwise.\r
	193	. EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one if\r
	194	a loopback is accomplished by software, 0 otherwise.\r
	195	. EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to\r
	196	one if the hardware flow control based on CTS (Clear\r
	197	To Send) and RTS (Ready To Send) control signals is\r
	198	enabled, 0 otherwise.\r
d2e7e385 RC	199	\r
d2e7e385 RC	200	@retval RETURN_SUCCESS The control bits were read from the serial device.\r
051e63bb	201	\r
	202	**/\r
	203	RETURN_STATUS\r
	204	EFIAPI\r
	205	PL011UartGetControl (\r
d2e7e385 RC	206	IN UINTN UartBase,\r
d2e7e385 RC	207	OUT UINT32 *Control\r
051e63bb	208	);\r
	209	\r
	210	/**\r
	211	Write data to serial device.\r
	212	\r
	213	@param Buffer Point of data buffer which need to be written.\r
	214	@param NumberOfBytes Number of output bytes which are cached in Buffer.\r
	215	\r
	216	@retval 0 Write data failed.\r
	217	@retval !0 Actual number of bytes written to serial device.\r
	218	\r
	219	**/\r
	220	UINTN\r
	221	EFIAPI\r
	222	PL011UartWrite (\r
	223	IN UINTN UartBase,\r
	224	IN UINT8 *Buffer,\r
	225	IN UINTN NumberOfBytes\r
	226	);\r
	227	\r
	228	/**\r
	229	Read data from serial device and save the data in buffer.\r
	230	\r
	231	@param Buffer Point of data buffer which need to be written.\r
	232	@param NumberOfBytes Number of output bytes which are cached in Buffer.\r
	233	\r
	234	@retval 0 Read data failed.\r
	235	@retval !0 Actual number of bytes read from serial device.\r
	236	\r
	237	**/\r
	238	UINTN\r
	239	EFIAPI\r
	240	PL011UartRead (\r
	241	IN UINTN UartBase,\r
	242	OUT UINT8 *Buffer,\r
	243	IN UINTN NumberOfBytes\r
	244	);\r
	245	\r
	246	/**\r
	247	Check to see if any data is available to be read from the debug device.\r
	248	\r
2d52a3a2 A	249	@retval TRUE At least one byte of data is available to be read\r
2d52a3a2 A	250	@retval FALSE No data is available to be read\r
051e63bb	251	\r
	252	**/\r
	253	BOOLEAN\r
	254	EFIAPI\r
	255	PL011UartPoll (\r
	256	IN UINTN UartBase\r
	257	);\r
	258	\r
	259	#endif\r