[mirror_edk2.git] / ArmPlatformPkg / Include / Drivers / PL011Uart.h

/** @file\r
*\r
*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
*\r
*  This program and the accompanying materials\r
*  are licensed and made available under the terms and conditions of the BSD License\r
*  which accompanies this distribution.  The full text of the license may be found at\r
*  http://opensource.org/licenses/bsd-license.php\r
*\r
*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
*\r
**/\r
\r
#ifndef __PL011_UART_H__\r
#define __PL011_UART_H__\r
\r
#include <Uefi.h>\r
#include <Protocol/SerialIo.h>\r
\r
// PL011 Registers\r
#define UARTDR                    0x000\r
#define UARTRSR                   0x004\r
#define UARTECR                   0x004\r
#define UARTFR                    0x018\r
#define UARTILPR                  0x020\r
#define UARTIBRD                  0x024\r
#define UARTFBRD                  0x028\r
#define UARTLCR_H                 0x02C\r
#define UARTCR                    0x030\r
#define UARTIFLS                  0x034\r
#define UARTIMSC                  0x038\r
#define UARTRIS                   0x03C\r
#define UARTMIS                   0x040\r
#define UARTICR                   0x044\r
#define UARTDMACR                 0x048\r
\r
#define UARTPID0                  0xFE0\r
#define UARTPID1                  0xFE4\r
#define UARTPID2                  0xFE8\r
#define UARTPID3                  0xFEC\r
\r
// Data status bits\r
#define UART_DATA_ERROR_MASK      0x0F00\r
\r
// Status reg bits\r
#define UART_STATUS_ERROR_MASK    0x0F\r
\r
// Flag reg bits\r
#define PL011_UARTFR_RI           (1 << 8)  // Ring indicator\r
#define PL011_UARTFR_TXFE         (1 << 7)  // Transmit FIFO empty\r
#define PL011_UARTFR_RXFF         (1 << 6)  // Receive  FIFO full\r
#define PL011_UARTFR_TXFF         (1 << 5)  // Transmit FIFO full\r
#define PL011_UARTFR_RXFE         (1 << 4)  // Receive  FIFO empty\r
#define PL011_UARTFR_BUSY         (1 << 3)  // UART busy\r
#define PL011_UARTFR_DCD          (1 << 2)  // Data carrier detect\r
#define PL011_UARTFR_DSR          (1 << 1)  // Data set ready\r
#define PL011_UARTFR_CTS          (1 << 0)  // Clear to send\r
\r
// Flag reg bits - alternative names\r
#define UART_TX_EMPTY_FLAG_MASK   PL011_UARTFR_TXFE\r
#define UART_RX_FULL_FLAG_MASK    PL011_UARTFR_RXFF\r
#define UART_TX_FULL_FLAG_MASK    PL011_UARTFR_TXFF\r
#define UART_RX_EMPTY_FLAG_MASK   PL011_UARTFR_RXFE\r
#define UART_BUSY_FLAG_MASK       PL011_UARTFR_BUSY\r
\r
// Control reg bits\r
#define PL011_UARTCR_CTSEN        (1 << 15) // CTS hardware flow control enable\r
#define PL011_UARTCR_RTSEN        (1 << 14) // RTS hardware flow control enable\r
#define PL011_UARTCR_RTS          (1 << 11) // Request to send\r
#define PL011_UARTCR_DTR          (1 << 10) // Data transmit ready.\r
#define PL011_UARTCR_RXE          (1 << 9)  // Receive enable\r
#define PL011_UARTCR_TXE          (1 << 8)  // Transmit enable\r
#define PL011_UARTCR_LBE          (1 << 7)  // Loopback enable\r
#define PL011_UARTCR_UARTEN       (1 << 0)  // UART Enable\r
\r
// Line Control Register Bits\r
#define PL011_UARTLCR_H_SPS       (1 << 7)  // Stick parity select\r
#define PL011_UARTLCR_H_WLEN_8    (3 << 5)\r
#define PL011_UARTLCR_H_WLEN_7    (2 << 5)\r
#define PL011_UARTLCR_H_WLEN_6    (1 << 5)\r
#define PL011_UARTLCR_H_WLEN_5    (0 << 5)\r
#define PL011_UARTLCR_H_FEN       (1 << 4)  // FIFOs Enable\r
#define PL011_UARTLCR_H_STP2      (1 << 3)  // Two stop bits select\r
#define PL011_UARTLCR_H_EPS       (1 << 2)  // Even parity select\r
#define PL011_UARTLCR_H_PEN       (1 << 1)  // Parity Enable\r
#define PL011_UARTLCR_H_BRK       (1 << 0)  // Send break\r
\r
#define PL011_UARTPID2_VER(X)     (((X) >> 4) & 0xF)\r
#define PL011_VER_R1P4            0x2\r
\r
/*\r
\r
  Programmed hardware of Serial port.\r
\r
  @return    Always return EFI_UNSUPPORTED.\r
\r
**/\r
RETURN_STATUS\r
EFIAPI\r
PL011UartInitializePort (\r
  IN OUT UINTN               UartBase,\r
  IN OUT UINT64              *BaudRate,\r
  IN OUT UINT32              *ReceiveFifoDepth,\r
  IN OUT EFI_PARITY_TYPE     *Parity,\r
  IN OUT UINT8               *DataBits,\r
  IN OUT EFI_STOP_BITS_TYPE  *StopBits\r
  );\r
\r
/**\r
\r
  Assert or deassert the control signals on a serial port.\r
  The following control signals are set according their bit settings :\r
  . Request to Send\r
  . Data Terminal Ready\r
\r
  @param[in]  UartBase  UART registers base address\r
  @param[in]  Control   The following bits are taken into account :\r
                        . EFI_SERIAL_REQUEST_TO_SEND : assert/deassert the\r
                          "Request To Send" control signal if this bit is\r
                          equal to one/zero.\r
                        . EFI_SERIAL_DATA_TERMINAL_READY : assert/deassert\r
                          the "Data Terminal Ready" control signal if this\r
                          bit is equal to one/zero.\r
                        . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/disable\r
                          the hardware loopback if this bit is equal to\r
                          one/zero.\r
                        . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supported.\r
                        . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enable/\r
                          disable the hardware flow control based on CTS (Clear\r
                          To Send) and RTS (Ready To Send) control signals.\r
\r
  @retval  RETURN_SUCCESS      The new control bits were set on the serial device.\r
  @retval  RETURN_UNSUPPORTED  The serial device does not support this operation.\r
\r
**/\r
RETURN_STATUS\r
EFIAPI\r
PL011UartSetControl (\r
  IN UINTN   UartBase,\r
  IN UINT32  Control\r
  );\r
\r
/**\r
\r
  Retrieve the status of the control bits on a serial device.\r
\r
  @param[in]   UartBase  UART registers base address\r
  @param[out]  Control   Status of the control bits on a serial device :\r
\r
                         . EFI_SERIAL_DATA_CLEAR_TO_SEND, EFI_SERIAL_DATA_SET_READY,\r
                           EFI_SERIAL_RING_INDICATE, EFI_SERIAL_CARRIER_DETECT,\r
                           EFI_SERIAL_REQUEST_TO_SEND, EFI_SERIAL_DATA_TERMINAL_READY\r
                           are all related to the DTE (Data Terminal Equipment) and\r
                           DCE (Data Communication Equipment) modes of operation of\r
                           the serial device.\r
                         . EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the receive\r
                           buffer is empty, 0 otherwise.\r
                         . EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the transmit\r
                           buffer is empty, 0 otherwise.\r
                         . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if the\r
                           hardware loopback is enabled (the ouput feeds the receive\r
                           buffer), 0 otherwise.\r
                         . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one if a\r
                           loopback is accomplished by software, 0 otherwise.\r
                         . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to one if the\r
                           hardware flow control based on CTS (Clear To Send) and RTS\r
                           (Ready To Send) control signals is enabled, 0 otherwise.\r
\r
\r
  @retval RETURN_SUCCESS  The control bits were read from the serial device.\r
\r
**/\r
RETURN_STATUS\r
EFIAPI\r
PL011UartGetControl (\r
  IN UINTN     UartBase,\r
  OUT UINT32  *Control\r
  );\r
\r
/**\r
  Write data to serial device.\r
\r
  @param  Buffer           Point of data buffer which need to be written.\r
  @param  NumberOfBytes    Number of output bytes which are cached in Buffer.\r
\r
  @retval 0                Write data failed.\r
  @retval !0               Actual number of bytes written to serial device.\r
\r
**/\r
UINTN\r
EFIAPI\r
PL011UartWrite (\r
  IN  UINTN       UartBase,\r
  IN  UINT8       *Buffer,\r
  IN  UINTN       NumberOfBytes\r
  );\r
\r
/**\r
  Read data from serial device and save the data in buffer.\r
\r
  @param  Buffer           Point of data buffer which need to be written.\r
  @param  NumberOfBytes    Number of output bytes which are cached in Buffer.\r
\r
  @retval 0                Read data failed.\r
  @retval !0               Actual number of bytes read from serial device.\r
\r
**/\r
UINTN\r
EFIAPI\r
PL011UartRead (\r
  IN  UINTN       UartBase,\r
  OUT UINT8       *Buffer,\r
  IN  UINTN       NumberOfBytes\r
  );\r
\r
/**\r
  Check to see if any data is available to be read from the debug device.\r
\r
  @retval EFI_SUCCESS       At least one byte of data is available to be read\r
  @retval EFI_NOT_READY     No data is available to be read\r
  @retval EFI_DEVICE_ERROR  The serial device is not functioning properly\r
\r
**/\r
BOOLEAN\r
EFIAPI\r
PL011UartPoll (\r
  IN  UINTN       UartBase\r
  );\r
\r
#endif\r
Commit	Line	Data
051e63bb	1	/** @file\r
051e63bb	2	*\r
ab716191	3	* Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
051e63bb	4	*\r
3402aac7 RC	5	* This program and the accompanying materials\r
	6	* are licensed and made available under the terms and conditions of the BSD License\r
	7	* which accompanies this distribution. The full text of the license may be found at\r
	8	* http://opensource.org/licenses/bsd-license.php\r
	9	*\r
	10	* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
051e63bb	12	*\r
	13	**/\r
	14	\r
	15	#ifndef __PL011_UART_H__\r
	16	#define __PL011_UART_H__\r
	17	\r
	18	#include <Uefi.h>\r
	19	#include <Protocol/SerialIo.h>\r
	20	\r
	21	// PL011 Registers\r
	22	#define UARTDR 0x000\r
	23	#define UARTRSR 0x004\r
	24	#define UARTECR 0x004\r
	25	#define UARTFR 0x018\r
	26	#define UARTILPR 0x020\r
	27	#define UARTIBRD 0x024\r
	28	#define UARTFBRD 0x028\r
	29	#define UARTLCR_H 0x02C\r
	30	#define UARTCR 0x030\r
	31	#define UARTIFLS 0x034\r
	32	#define UARTIMSC 0x038\r
	33	#define UARTRIS 0x03C\r
	34	#define UARTMIS 0x040\r
	35	#define UARTICR 0x044\r
	36	#define UARTDMACR 0x048\r
	37	\r
48edf6be LL	38	#define UARTPID0 0xFE0\r
	39	#define UARTPID1 0xFE4\r
	40	#define UARTPID2 0xFE8\r
	41	#define UARTPID3 0xFEC\r
	42	\r
051e63bb	43	// Data status bits\r
	44	#define UART_DATA_ERROR_MASK 0x0F00\r
	45	\r
	46	// Status reg bits\r
	47	#define UART_STATUS_ERROR_MASK 0x0F\r
	48	\r
	49	// Flag reg bits\r
	50	#define PL011_UARTFR_RI (1 << 8) // Ring indicator\r
	51	#define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty\r
	52	#define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full\r
	53	#define PL011_UARTFR_TXFF (1 << 5) // Transmit FIFO full\r
	54	#define PL011_UARTFR_RXFE (1 << 4) // Receive FIFO empty\r
	55	#define PL011_UARTFR_BUSY (1 << 3) // UART busy\r
	56	#define PL011_UARTFR_DCD (1 << 2) // Data carrier detect\r
	57	#define PL011_UARTFR_DSR (1 << 1) // Data set ready\r
	58	#define PL011_UARTFR_CTS (1 << 0) // Clear to send\r
	59	\r
	60	// Flag reg bits - alternative names\r
	61	#define UART_TX_EMPTY_FLAG_MASK PL011_UARTFR_TXFE\r
	62	#define UART_RX_FULL_FLAG_MASK PL011_UARTFR_RXFF\r
	63	#define UART_TX_FULL_FLAG_MASK PL011_UARTFR_TXFF\r
	64	#define UART_RX_EMPTY_FLAG_MASK PL011_UARTFR_RXFE\r
	65	#define UART_BUSY_FLAG_MASK PL011_UARTFR_BUSY\r
	66	\r
	67	// Control reg bits\r
	68	#define PL011_UARTCR_CTSEN (1 << 15) // CTS hardware flow control enable\r
	69	#define PL011_UARTCR_RTSEN (1 << 14) // RTS hardware flow control enable\r
	70	#define PL011_UARTCR_RTS (1 << 11) // Request to send\r
	71	#define PL011_UARTCR_DTR (1 << 10) // Data transmit ready.\r
	72	#define PL011_UARTCR_RXE (1 << 9) // Receive enable\r
	73	#define PL011_UARTCR_TXE (1 << 8) // Transmit enable\r
	74	#define PL011_UARTCR_LBE (1 << 7) // Loopback enable\r
	75	#define PL011_UARTCR_UARTEN (1 << 0) // UART Enable\r
	76	\r
	77	// Line Control Register Bits\r
	78	#define PL011_UARTLCR_H_SPS (1 << 7) // Stick parity select\r
	79	#define PL011_UARTLCR_H_WLEN_8 (3 << 5)\r
	80	#define PL011_UARTLCR_H_WLEN_7 (2 << 5)\r
	81	#define PL011_UARTLCR_H_WLEN_6 (1 << 5)\r
	82	#define PL011_UARTLCR_H_WLEN_5 (0 << 5)\r
	83	#define PL011_UARTLCR_H_FEN (1 << 4) // FIFOs Enable\r
	84	#define PL011_UARTLCR_H_STP2 (1 << 3) // Two stop bits select\r
	85	#define PL011_UARTLCR_H_EPS (1 << 2) // Even parity select\r
	86	#define PL011_UARTLCR_H_PEN (1 << 1) // Parity Enable\r
	87	#define PL011_UARTLCR_H_BRK (1 << 0) // Send break\r
	88	\r
48edf6be LL	89	#define PL011_UARTPID2_VER(X) (((X) >> 4) & 0xF)\r
	90	#define PL011_VER_R1P4 0x2\r
	91	\r
051e63bb	92	/*\r
	93	\r
	94	Programmed hardware of Serial port.\r
	95	\r
	96	@return Always return EFI_UNSUPPORTED.\r
	97	\r
	98	**/\r
	99	RETURN_STATUS\r
	100	EFIAPI\r
	101	PL011UartInitializePort (\r
15e277d5	102	IN OUT UINTN UartBase,\r
	103	IN OUT UINT64 *BaudRate,\r
	104	IN OUT UINT32 *ReceiveFifoDepth,\r
	105	IN OUT EFI_PARITY_TYPE *Parity,\r
	106	IN OUT UINT8 *DataBits,\r
	107	IN OUT EFI_STOP_BITS_TYPE *StopBits\r
051e63bb	108	);\r
	109	\r
	110	/**\r
051e63bb	111	\r
ab716191 RC	112	Assert or deassert the control signals on a serial port.\r
	113	The following control signals are set according their bit settings :\r
	114	. Request to Send\r
	115	. Data Terminal Ready\r
	116	\r
	117	@param[in] UartBase UART registers base address\r
	118	@param[in] Control The following bits are taken into account :\r
	119	. EFI_SERIAL_REQUEST_TO_SEND : assert/deassert the\r
	120	"Request To Send" control signal if this bit is\r
	121	equal to one/zero.\r
	122	. EFI_SERIAL_DATA_TERMINAL_READY : assert/deassert\r
	123	the "Data Terminal Ready" control signal if this\r
	124	bit is equal to one/zero.\r
	125	. EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/disable\r
	126	the hardware loopback if this bit is equal to\r
	127	one/zero.\r
	128	. EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supported.\r
	129	. EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enable/\r
	130	disable the hardware flow control based on CTS (Clear\r
	131	To Send) and RTS (Ready To Send) control signals.\r
	132	\r
	133	@retval RETURN_SUCCESS The new control bits were set on the serial device.\r
	134	@retval RETURN_UNSUPPORTED The serial device does not support this operation.\r
051e63bb	135	\r
	136	**/\r
	137	RETURN_STATUS\r
	138	EFIAPI\r
	139	PL011UartSetControl (\r
ab716191 RC	140	IN UINTN UartBase,\r
ab716191 RC	141	IN UINT32 Control\r
051e63bb	142	);\r
	143	\r
	144	/**\r
051e63bb	145	\r
d2e7e385 RC	146	Retrieve the status of the control bits on a serial device.\r
	147	\r
	148	@param[in] UartBase UART registers base address\r
	149	@param[out] Control Status of the control bits on a serial device :\r
	150	\r
	151	. EFI_SERIAL_DATA_CLEAR_TO_SEND, EFI_SERIAL_DATA_SET_READY,\r
	152	EFI_SERIAL_RING_INDICATE, EFI_SERIAL_CARRIER_DETECT,\r
	153	EFI_SERIAL_REQUEST_TO_SEND, EFI_SERIAL_DATA_TERMINAL_READY\r
	154	are all related to the DTE (Data Terminal Equipment) and\r
	155	DCE (Data Communication Equipment) modes of operation of\r
	156	the serial device.\r
	157	. EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the receive\r
	158	buffer is empty, 0 otherwise.\r
	159	. EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the transmit\r
	160	buffer is empty, 0 otherwise.\r
	161	. EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if the\r
	162	hardware loopback is enabled (the ouput feeds the receive\r
	163	buffer), 0 otherwise.\r
	164	. EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one if a\r
	165	loopback is accomplished by software, 0 otherwise.\r
	166	. EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to one if the\r
	167	hardware flow control based on CTS (Clear To Send) and RTS\r
	168	(Ready To Send) control signals is enabled, 0 otherwise.\r
	169	\r
	170	\r
	171	@retval RETURN_SUCCESS The control bits were read from the serial device.\r
051e63bb	172	\r
	173	**/\r
	174	RETURN_STATUS\r
	175	EFIAPI\r
	176	PL011UartGetControl (\r
d2e7e385 RC	177	IN UINTN UartBase,\r
d2e7e385 RC	178	OUT UINT32 *Control\r
051e63bb	179	);\r
	180	\r
	181	/**\r
	182	Write data to serial device.\r
	183	\r
	184	@param Buffer Point of data buffer which need to be written.\r
	185	@param NumberOfBytes Number of output bytes which are cached in Buffer.\r
	186	\r
	187	@retval 0 Write data failed.\r
	188	@retval !0 Actual number of bytes written to serial device.\r
	189	\r
	190	**/\r
	191	UINTN\r
	192	EFIAPI\r
	193	PL011UartWrite (\r
	194	IN UINTN UartBase,\r
	195	IN UINT8 *Buffer,\r
	196	IN UINTN NumberOfBytes\r
	197	);\r
	198	\r
	199	/**\r
	200	Read data from serial device and save the data in buffer.\r
	201	\r
	202	@param Buffer Point of data buffer which need to be written.\r
	203	@param NumberOfBytes Number of output bytes which are cached in Buffer.\r
	204	\r
	205	@retval 0 Read data failed.\r
	206	@retval !0 Actual number of bytes read from serial device.\r
	207	\r
	208	**/\r
	209	UINTN\r
	210	EFIAPI\r
	211	PL011UartRead (\r
	212	IN UINTN UartBase,\r
	213	OUT UINT8 *Buffer,\r
	214	IN UINTN NumberOfBytes\r
	215	);\r
	216	\r
	217	/**\r
	218	Check to see if any data is available to be read from the debug device.\r
	219	\r
	220	@retval EFI_SUCCESS At least one byte of data is available to be read\r
	221	@retval EFI_NOT_READY No data is available to be read\r
	222	@retval EFI_DEVICE_ERROR The serial device is not functioning properly\r
	223	\r
	224	**/\r
	225	BOOLEAN\r
	226	EFIAPI\r
	227	PL011UartPoll (\r
	228	IN UINTN UartBase\r
	229	);\r
	230	\r
	231	#endif\r