[mirror_edk2.git] / ArmPlatformPkg / Include / Drivers / PL011Uart.h

/** @file\r
*\r
*  Copyright (c) 2011-2016, ARM Limited. All rights reserved.\r
*\r
*  This program and the accompanying materials\r
*  are licensed and made available under the terms and conditions of the BSD License\r
*  which accompanies this distribution.  The full text of the license may be found at\r
*  http://opensource.org/licenses/bsd-license.php\r
*\r
*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
*\r
**/\r
\r
#ifndef __PL011_UART_H__\r
#define __PL011_UART_H__\r
\r
#include <Uefi.h>\r
#include <Protocol/SerialIo.h>\r
\r
#define PL011_VARIANT_ZTE 1\r
\r
// PL011 Registers\r
#if FixedPcdGet8 (PL011UartRegOffsetVariant) == PL011_VARIANT_ZTE\r
#define UARTDR                    0x004\r
#define UARTRSR                   0x010\r
#define UARTECR                   0x010\r
#define UARTFR                    0x014\r
#define UARTIBRD                  0x024\r
#define UARTFBRD                  0x028\r
#define UARTLCR_H                 0x030\r
#define UARTCR                    0x034\r
#define UARTIFLS                  0x038\r
#define UARTIMSC                  0x040\r
#define UARTRIS                   0x044\r
#define UARTMIS                   0x048\r
#define UARTICR                   0x04c\r
#define UARTDMACR                 0x050\r
#else\r
#define UARTDR                    0x000\r
#define UARTRSR                   0x004\r
#define UARTECR                   0x004\r
#define UARTFR                    0x018\r
#define UARTILPR                  0x020\r
#define UARTIBRD                  0x024\r
#define UARTFBRD                  0x028\r
#define UARTLCR_H                 0x02C\r
#define UARTCR                    0x030\r
#define UARTIFLS                  0x034\r
#define UARTIMSC                  0x038\r
#define UARTRIS                   0x03C\r
#define UARTMIS                   0x040\r
#define UARTICR                   0x044\r
#define UARTDMACR                 0x048\r
#endif\r
\r
#define UARTPID0                  0xFE0\r
#define UARTPID1                  0xFE4\r
#define UARTPID2                  0xFE8\r
#define UARTPID3                  0xFEC\r
\r
// Data status bits\r
#define UART_DATA_ERROR_MASK      0x0F00\r
\r
// Status reg bits\r
#define UART_STATUS_ERROR_MASK    0x0F\r
\r
// Flag reg bits\r
#if FixedPcdGet8 (PL011UartRegOffsetVariant) == PL011_VARIANT_ZTE\r
#define PL011_UARTFR_RI           (1 << 0)  // Ring indicator\r
#define PL011_UARTFR_TXFE         (1 << 7)  // Transmit FIFO empty\r
#define PL011_UARTFR_RXFF         (1 << 6)  // Receive  FIFO full\r
#define PL011_UARTFR_TXFF         (1 << 5)  // Transmit FIFO full\r
#define PL011_UARTFR_RXFE         (1 << 4)  // Receive  FIFO empty\r
#define PL011_UARTFR_BUSY         (1 << 8)  // UART busy\r
#define PL011_UARTFR_DCD          (1 << 2)  // Data carrier detect\r
#define PL011_UARTFR_DSR          (1 << 3)  // Data set ready\r
#define PL011_UARTFR_CTS          (1 << 1)  // Clear to send\r
#else\r
#define PL011_UARTFR_RI           (1 << 8)  // Ring indicator\r
#define PL011_UARTFR_TXFE         (1 << 7)  // Transmit FIFO empty\r
#define PL011_UARTFR_RXFF         (1 << 6)  // Receive  FIFO full\r
#define PL011_UARTFR_TXFF         (1 << 5)  // Transmit FIFO full\r
#define PL011_UARTFR_RXFE         (1 << 4)  // Receive  FIFO empty\r
#define PL011_UARTFR_BUSY         (1 << 3)  // UART busy\r
#define PL011_UARTFR_DCD          (1 << 2)  // Data carrier detect\r
#define PL011_UARTFR_DSR          (1 << 1)  // Data set ready\r
#define PL011_UARTFR_CTS          (1 << 0)  // Clear to send\r
#endif\r
\r
// Flag reg bits - alternative names\r
#define UART_TX_EMPTY_FLAG_MASK   PL011_UARTFR_TXFE\r
#define UART_RX_FULL_FLAG_MASK    PL011_UARTFR_RXFF\r
#define UART_TX_FULL_FLAG_MASK    PL011_UARTFR_TXFF\r
#define UART_RX_EMPTY_FLAG_MASK   PL011_UARTFR_RXFE\r
#define UART_BUSY_FLAG_MASK       PL011_UARTFR_BUSY\r
\r
// Control reg bits\r
#define PL011_UARTCR_CTSEN        (1 << 15) // CTS hardware flow control enable\r
#define PL011_UARTCR_RTSEN        (1 << 14) // RTS hardware flow control enable\r
#define PL011_UARTCR_RTS          (1 << 11) // Request to send\r
#define PL011_UARTCR_DTR          (1 << 10) // Data transmit ready.\r
#define PL011_UARTCR_RXE          (1 << 9)  // Receive enable\r
#define PL011_UARTCR_TXE          (1 << 8)  // Transmit enable\r
#define PL011_UARTCR_LBE          (1 << 7)  // Loopback enable\r
#define PL011_UARTCR_UARTEN       (1 << 0)  // UART Enable\r
\r
// Line Control Register Bits\r
#define PL011_UARTLCR_H_SPS       (1 << 7)  // Stick parity select\r
#define PL011_UARTLCR_H_WLEN_8    (3 << 5)\r
#define PL011_UARTLCR_H_WLEN_7    (2 << 5)\r
#define PL011_UARTLCR_H_WLEN_6    (1 << 5)\r
#define PL011_UARTLCR_H_WLEN_5    (0 << 5)\r
#define PL011_UARTLCR_H_FEN       (1 << 4)  // FIFOs Enable\r
#define PL011_UARTLCR_H_STP2      (1 << 3)  // Two stop bits select\r
#define PL011_UARTLCR_H_EPS       (1 << 2)  // Even parity select\r
#define PL011_UARTLCR_H_PEN       (1 << 1)  // Parity Enable\r
#define PL011_UARTLCR_H_BRK       (1 << 0)  // Send break\r
\r
#define PL011_UARTPID2_VER(X)     (((X) >> 4) & 0xF)\r
#define PL011_VER_R1P4            0x2\r
\r
/**\r
\r
  Initialise the serial port to the specified settings.\r
  All unspecified settings will be set to the default values.\r
\r
  @param[in]  UartBase            The base address of the serial device.\r
  @param[in]  UartClkInHz         The clock in Hz for the serial device.\r
                                  Ignored if the PCD PL011UartInteger is not 0\r
  @param[in out] BaudRate         The baud rate of the serial device. If the\r
                                  baud rate is not supported, the speed will be\r
                                  reduced to the nearest supported one and the\r
                                  variable's value will be updated accordingly.\r
  @param[in out] ReceiveFifoDepth The number of characters the device will\r
                                  buffer on input.  Value of 0 will use the\r
                                  device's default FIFO depth.\r
  @param[in out]  Parity          If applicable, this is the EFI_PARITY_TYPE\r
                                  that is computed or checked as each character\r
                                  is transmitted or received. If the device\r
                                  does not support parity, the value is the\r
                                  default parity value.\r
  @param[in out]  DataBits        The number of data bits in each character.\r
  @param[in out]  StopBits        If applicable, the EFI_STOP_BITS_TYPE number\r
                                  of stop bits per character.\r
                                  If the device does not support stop bits, the\r
                                  value is the default stop bit value.\r
\r
  @retval RETURN_SUCCESS            All attributes were set correctly on the\r
                                    serial device.\r
  @retval RETURN_INVALID_PARAMETER  One or more of the attributes has an\r
                                    unsupported value.\r
\r
**/\r
RETURN_STATUS\r
EFIAPI\r
PL011UartInitializePort (\r
  IN     UINTN               UartBase,\r
  IN     UINT32              UartClkInHz,\r
  IN OUT UINT64              *BaudRate,\r
  IN OUT UINT32              *ReceiveFifoDepth,\r
  IN OUT EFI_PARITY_TYPE     *Parity,\r
  IN OUT UINT8               *DataBits,\r
  IN OUT EFI_STOP_BITS_TYPE  *StopBits\r
  );\r
\r
/**\r
\r
  Assert or deassert the control signals on a serial port.\r
  The following control signals are set according their bit settings :\r
  . Request to Send\r
  . Data Terminal Ready\r
\r
  @param[in]  UartBase  UART registers base address\r
  @param[in]  Control   The following bits are taken into account :\r
                        . EFI_SERIAL_REQUEST_TO_SEND : assert/deassert the\r
                          "Request To Send" control signal if this bit is\r
                          equal to one/zero.\r
                        . EFI_SERIAL_DATA_TERMINAL_READY : assert/deassert\r
                          the "Data Terminal Ready" control signal if this\r
                          bit is equal to one/zero.\r
                        . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/disable\r
                          the hardware loopback if this bit is equal to\r
                          one/zero.\r
                        . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supported.\r
                        . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enable/\r
                          disable the hardware flow control based on CTS (Clear\r
                          To Send) and RTS (Ready To Send) control signals.\r
\r
  @retval  RETURN_SUCCESS      The new control bits were set on the device.\r
  @retval  RETURN_UNSUPPORTED  The device does not support this operation.\r
\r
**/\r
RETURN_STATUS\r
EFIAPI\r
PL011UartSetControl (\r
  IN UINTN   UartBase,\r
  IN UINT32  Control\r
  );\r
\r
/**\r
\r
  Retrieve the status of the control bits on a serial device.\r
\r
  @param[in]   UartBase  UART registers base address\r
  @param[out]  Control   Status of the control bits on a serial device :\r
\r
                         . EFI_SERIAL_DATA_CLEAR_TO_SEND,\r
                           EFI_SERIAL_DATA_SET_READY,\r
                           EFI_SERIAL_RING_INDICATE,\r
                           EFI_SERIAL_CARRIER_DETECT,\r
                           EFI_SERIAL_REQUEST_TO_SEND,\r
                           EFI_SERIAL_DATA_TERMINAL_READY\r
                           are all related to the DTE (Data Terminal Equipment)\r
                           and DCE (Data Communication Equipment) modes of\r
                           operation of the serial device.\r
                         . EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the\r
                           receive buffer is empty, 0 otherwise.\r
                         . EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the\r
                           transmit buffer is empty, 0 otherwise.\r
                         . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if\r
                           the hardware loopback is enabled (the ouput feeds the\r
                           receive buffer), 0 otherwise.\r
                         . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one if\r
                           a loopback is accomplished by software, 0 otherwise.\r
                         . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to\r
                           one if the hardware flow control based on CTS (Clear\r
                           To Send) and RTS (Ready To Send) control signals is\r
                           enabled, 0 otherwise.\r
\r
  @retval RETURN_SUCCESS  The control bits were read from the serial device.\r
\r
**/\r
RETURN_STATUS\r
EFIAPI\r
PL011UartGetControl (\r
  IN UINTN     UartBase,\r
  OUT UINT32  *Control\r
  );\r
\r
/**\r
  Write data to serial device.\r
\r
  @param  Buffer           Point of data buffer which need to be written.\r
  @param  NumberOfBytes    Number of output bytes which are cached in Buffer.\r
\r
  @retval 0                Write data failed.\r
  @retval !0               Actual number of bytes written to serial device.\r
\r
**/\r
UINTN\r
EFIAPI\r
PL011UartWrite (\r
  IN  UINTN       UartBase,\r
  IN  UINT8       *Buffer,\r
  IN  UINTN       NumberOfBytes\r
  );\r
\r
/**\r
  Read data from serial device and save the data in buffer.\r
\r
  @param  Buffer           Point of data buffer which need to be written.\r
  @param  NumberOfBytes    Number of output bytes which are cached in Buffer.\r
\r
  @retval 0                Read data failed.\r
  @retval !0               Actual number of bytes read from serial device.\r
\r
**/\r
UINTN\r
EFIAPI\r
PL011UartRead (\r
  IN  UINTN       UartBase,\r
  OUT UINT8       *Buffer,\r
  IN  UINTN       NumberOfBytes\r
  );\r
\r
/**\r
  Check to see if any data is available to be read from the debug device.\r
\r
  @retval TRUE       At least one byte of data is available to be read\r
  @retval FALSE      No data is available to be read\r
\r
**/\r
BOOLEAN\r
EFIAPI\r
PL011UartPoll (\r
  IN  UINTN       UartBase\r
  );\r
\r
#endif\r
Commit	Line	Data
051e63bb	1	/** @file\r
051e63bb	2	*\r
9f08a052	3	* Copyright (c) 2011-2016, ARM Limited. All rights reserved.\r
051e63bb	4	*\r
3402aac7 RC	5	* This program and the accompanying materials\r
	6	* are licensed and made available under the terms and conditions of the BSD License\r
	7	* which accompanies this distribution. The full text of the license may be found at\r
	8	* http://opensource.org/licenses/bsd-license.php\r
	9	*\r
	10	* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
051e63bb	12	*\r
	13	**/\r
	14	\r
	15	#ifndef __PL011_UART_H__\r
	16	#define __PL011_UART_H__\r
	17	\r
	18	#include <Uefi.h>\r
	19	#include <Protocol/SerialIo.h>\r
	20	\r
d4f6c35c JN	21	#define PL011_VARIANT_ZTE 1\r
d4f6c35c JN	22	\r
051e63bb	23	// PL011 Registers\r
d4f6c35c JN	24	#if FixedPcdGet8 (PL011UartRegOffsetVariant) == PL011_VARIANT_ZTE\r
	25	#define UARTDR 0x004\r
	26	#define UARTRSR 0x010\r
	27	#define UARTECR 0x010\r
	28	#define UARTFR 0x014\r
	29	#define UARTIBRD 0x024\r
	30	#define UARTFBRD 0x028\r
	31	#define UARTLCR_H 0x030\r
	32	#define UARTCR 0x034\r
	33	#define UARTIFLS 0x038\r
	34	#define UARTIMSC 0x040\r
	35	#define UARTRIS 0x044\r
	36	#define UARTMIS 0x048\r
	37	#define UARTICR 0x04c\r
	38	#define UARTDMACR 0x050\r
	39	#else\r
051e63bb	40	#define UARTDR 0x000\r
	41	#define UARTRSR 0x004\r
	42	#define UARTECR 0x004\r
	43	#define UARTFR 0x018\r
	44	#define UARTILPR 0x020\r
	45	#define UARTIBRD 0x024\r
	46	#define UARTFBRD 0x028\r
	47	#define UARTLCR_H 0x02C\r
	48	#define UARTCR 0x030\r
	49	#define UARTIFLS 0x034\r
	50	#define UARTIMSC 0x038\r
	51	#define UARTRIS 0x03C\r
	52	#define UARTMIS 0x040\r
	53	#define UARTICR 0x044\r
	54	#define UARTDMACR 0x048\r
d4f6c35c	55	#endif\r
051e63bb	56	\r
48edf6be LL	57	#define UARTPID0 0xFE0\r
	58	#define UARTPID1 0xFE4\r
	59	#define UARTPID2 0xFE8\r
	60	#define UARTPID3 0xFEC\r
	61	\r
051e63bb	62	// Data status bits\r
	63	#define UART_DATA_ERROR_MASK 0x0F00\r
	64	\r
	65	// Status reg bits\r
	66	#define UART_STATUS_ERROR_MASK 0x0F\r
	67	\r
	68	// Flag reg bits\r
d4f6c35c JN	69	#if FixedPcdGet8 (PL011UartRegOffsetVariant) == PL011_VARIANT_ZTE\r
	70	#define PL011_UARTFR_RI (1 << 0) // Ring indicator\r
	71	#define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty\r
	72	#define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full\r
	73	#define PL011_UARTFR_TXFF (1 << 5) // Transmit FIFO full\r
	74	#define PL011_UARTFR_RXFE (1 << 4) // Receive FIFO empty\r
	75	#define PL011_UARTFR_BUSY (1 << 8) // UART busy\r
	76	#define PL011_UARTFR_DCD (1 << 2) // Data carrier detect\r
	77	#define PL011_UARTFR_DSR (1 << 3) // Data set ready\r
	78	#define PL011_UARTFR_CTS (1 << 1) // Clear to send\r
	79	#else\r
051e63bb	80	#define PL011_UARTFR_RI (1 << 8) // Ring indicator\r
	81	#define PL011_UARTFR_TXFE (1 << 7) // Transmit FIFO empty\r
	82	#define PL011_UARTFR_RXFF (1 << 6) // Receive FIFO full\r
	83	#define PL011_UARTFR_TXFF (1 << 5) // Transmit FIFO full\r
	84	#define PL011_UARTFR_RXFE (1 << 4) // Receive FIFO empty\r
	85	#define PL011_UARTFR_BUSY (1 << 3) // UART busy\r
	86	#define PL011_UARTFR_DCD (1 << 2) // Data carrier detect\r
	87	#define PL011_UARTFR_DSR (1 << 1) // Data set ready\r
	88	#define PL011_UARTFR_CTS (1 << 0) // Clear to send\r
d4f6c35c	89	#endif\r
051e63bb	90	\r
	91	// Flag reg bits - alternative names\r
	92	#define UART_TX_EMPTY_FLAG_MASK PL011_UARTFR_TXFE\r
	93	#define UART_RX_FULL_FLAG_MASK PL011_UARTFR_RXFF\r
	94	#define UART_TX_FULL_FLAG_MASK PL011_UARTFR_TXFF\r
	95	#define UART_RX_EMPTY_FLAG_MASK PL011_UARTFR_RXFE\r
	96	#define UART_BUSY_FLAG_MASK PL011_UARTFR_BUSY\r
	97	\r
	98	// Control reg bits\r
	99	#define PL011_UARTCR_CTSEN (1 << 15) // CTS hardware flow control enable\r
	100	#define PL011_UARTCR_RTSEN (1 << 14) // RTS hardware flow control enable\r
	101	#define PL011_UARTCR_RTS (1 << 11) // Request to send\r
	102	#define PL011_UARTCR_DTR (1 << 10) // Data transmit ready.\r
	103	#define PL011_UARTCR_RXE (1 << 9) // Receive enable\r
	104	#define PL011_UARTCR_TXE (1 << 8) // Transmit enable\r
	105	#define PL011_UARTCR_LBE (1 << 7) // Loopback enable\r
	106	#define PL011_UARTCR_UARTEN (1 << 0) // UART Enable\r
	107	\r
	108	// Line Control Register Bits\r
	109	#define PL011_UARTLCR_H_SPS (1 << 7) // Stick parity select\r
	110	#define PL011_UARTLCR_H_WLEN_8 (3 << 5)\r
	111	#define PL011_UARTLCR_H_WLEN_7 (2 << 5)\r
	112	#define PL011_UARTLCR_H_WLEN_6 (1 << 5)\r
	113	#define PL011_UARTLCR_H_WLEN_5 (0 << 5)\r
	114	#define PL011_UARTLCR_H_FEN (1 << 4) // FIFOs Enable\r
	115	#define PL011_UARTLCR_H_STP2 (1 << 3) // Two stop bits select\r
	116	#define PL011_UARTLCR_H_EPS (1 << 2) // Even parity select\r
	117	#define PL011_UARTLCR_H_PEN (1 << 1) // Parity Enable\r
	118	#define PL011_UARTLCR_H_BRK (1 << 0) // Send break\r
	119	\r
48edf6be LL	120	#define PL011_UARTPID2_VER(X) (((X) >> 4) & 0xF)\r
	121	#define PL011_VER_R1P4 0x2\r
	122	\r
f6300528	123	/**\r
051e63bb	124	\r
9f08a052 EL	125	Initialise the serial port to the specified settings.\r
	126	All unspecified settings will be set to the default values.\r
	127	\r
f6300528 EL	128	@param[in] UartBase The base address of the serial device.\r
	129	@param[in] UartClkInHz The clock in Hz for the serial device.\r
	130	Ignored if the PCD PL011UartInteger is not 0\r
	131	@param[in out] BaudRate The baud rate of the serial device. If the\r
9f08a052 EL	132	baud rate is not supported, the speed will be\r
	133	reduced to the nearest supported one and the\r
	134	variable's value will be updated accordingly.\r
f6300528	135	@param[in out] ReceiveFifoDepth The number of characters the device will\r
9f08a052 EL	136	buffer on input. Value of 0 will use the\r
9f08a052 EL	137	device's default FIFO depth.\r
f6300528	138	@param[in out] Parity If applicable, this is the EFI_PARITY_TYPE\r
9f08a052 EL	139	that is computed or checked as each character\r
	140	is transmitted or received. If the device\r
	141	does not support parity, the value is the\r
	142	default parity value.\r
f6300528 EL	143	@param[in out] DataBits The number of data bits in each character.\r
f6300528 EL	144	@param[in out] StopBits If applicable, the EFI_STOP_BITS_TYPE number\r
9f08a052 EL	145	of stop bits per character.\r
	146	If the device does not support stop bits, the\r
	147	value is the default stop bit value.\r
	148	\r
	149	@retval RETURN_SUCCESS All attributes were set correctly on the\r
	150	serial device.\r
	151	@retval RETURN_INVALID_PARAMETER One or more of the attributes has an\r
	152	unsupported value.\r
051e63bb	153	\r
	154	**/\r
	155	RETURN_STATUS\r
	156	EFIAPI\r
	157	PL011UartInitializePort (\r
9f08a052	158	IN UINTN UartBase,\r
f6300528	159	IN UINT32 UartClkInHz,\r
15e277d5	160	IN OUT UINT64 *BaudRate,\r
	161	IN OUT UINT32 *ReceiveFifoDepth,\r
	162	IN OUT EFI_PARITY_TYPE *Parity,\r
	163	IN OUT UINT8 *DataBits,\r
	164	IN OUT EFI_STOP_BITS_TYPE *StopBits\r
051e63bb	165	);\r
	166	\r
	167	/**\r
051e63bb	168	\r
ab716191 RC	169	Assert or deassert the control signals on a serial port.\r
	170	The following control signals are set according their bit settings :\r
	171	. Request to Send\r
	172	. Data Terminal Ready\r
	173	\r
	174	@param[in] UartBase UART registers base address\r
	175	@param[in] Control The following bits are taken into account :\r
	176	. EFI_SERIAL_REQUEST_TO_SEND : assert/deassert the\r
	177	"Request To Send" control signal if this bit is\r
	178	equal to one/zero.\r
	179	. EFI_SERIAL_DATA_TERMINAL_READY : assert/deassert\r
	180	the "Data Terminal Ready" control signal if this\r
	181	bit is equal to one/zero.\r
	182	. EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/disable\r
	183	the hardware loopback if this bit is equal to\r
	184	one/zero.\r
	185	. EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supported.\r
	186	. EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enable/\r
	187	disable the hardware flow control based on CTS (Clear\r
	188	To Send) and RTS (Ready To Send) control signals.\r
	189	\r
9f08a052 EL	190	@retval RETURN_SUCCESS The new control bits were set on the device.\r
9f08a052 EL	191	@retval RETURN_UNSUPPORTED The device does not support this operation.\r
051e63bb	192	\r
	193	**/\r
	194	RETURN_STATUS\r
	195	EFIAPI\r
	196	PL011UartSetControl (\r
ab716191 RC	197	IN UINTN UartBase,\r
ab716191 RC	198	IN UINT32 Control\r
051e63bb	199	);\r
	200	\r
	201	/**\r
051e63bb	202	\r
d2e7e385 RC	203	Retrieve the status of the control bits on a serial device.\r
	204	\r
	205	@param[in] UartBase UART registers base address\r
	206	@param[out] Control Status of the control bits on a serial device :\r
	207	\r
9f08a052 EL	208	. EFI_SERIAL_DATA_CLEAR_TO_SEND,\r
	209	EFI_SERIAL_DATA_SET_READY,\r
	210	EFI_SERIAL_RING_INDICATE,\r
	211	EFI_SERIAL_CARRIER_DETECT,\r
	212	EFI_SERIAL_REQUEST_TO_SEND,\r
	213	EFI_SERIAL_DATA_TERMINAL_READY\r
	214	are all related to the DTE (Data Terminal Equipment)\r
	215	and DCE (Data Communication Equipment) modes of\r
	216	operation of the serial device.\r
	217	. EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the\r
	218	receive buffer is empty, 0 otherwise.\r
	219	. EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the\r
	220	transmit buffer is empty, 0 otherwise.\r
	221	. EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if\r
	222	the hardware loopback is enabled (the ouput feeds the\r
	223	receive buffer), 0 otherwise.\r
	224	. EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one if\r
	225	a loopback is accomplished by software, 0 otherwise.\r
	226	. EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to\r
	227	one if the hardware flow control based on CTS (Clear\r
	228	To Send) and RTS (Ready To Send) control signals is\r
	229	enabled, 0 otherwise.\r
d2e7e385 RC	230	\r
d2e7e385 RC	231	@retval RETURN_SUCCESS The control bits were read from the serial device.\r
051e63bb	232	\r
	233	**/\r
	234	RETURN_STATUS\r
	235	EFIAPI\r
	236	PL011UartGetControl (\r
d2e7e385 RC	237	IN UINTN UartBase,\r
d2e7e385 RC	238	OUT UINT32 *Control\r
051e63bb	239	);\r
	240	\r
	241	/**\r
	242	Write data to serial device.\r
	243	\r
	244	@param Buffer Point of data buffer which need to be written.\r
	245	@param NumberOfBytes Number of output bytes which are cached in Buffer.\r
	246	\r
	247	@retval 0 Write data failed.\r
	248	@retval !0 Actual number of bytes written to serial device.\r
	249	\r
	250	**/\r
	251	UINTN\r
	252	EFIAPI\r
	253	PL011UartWrite (\r
	254	IN UINTN UartBase,\r
	255	IN UINT8 *Buffer,\r
	256	IN UINTN NumberOfBytes\r
	257	);\r
	258	\r
	259	/**\r
	260	Read data from serial device and save the data in buffer.\r
	261	\r
	262	@param Buffer Point of data buffer which need to be written.\r
	263	@param NumberOfBytes Number of output bytes which are cached in Buffer.\r
	264	\r
	265	@retval 0 Read data failed.\r
	266	@retval !0 Actual number of bytes read from serial device.\r
	267	\r
	268	**/\r
	269	UINTN\r
	270	EFIAPI\r
	271	PL011UartRead (\r
	272	IN UINTN UartBase,\r
	273	OUT UINT8 *Buffer,\r
	274	IN UINTN NumberOfBytes\r
	275	);\r
	276	\r
	277	/**\r
	278	Check to see if any data is available to be read from the debug device.\r
	279	\r
2d52a3a2 A	280	@retval TRUE At least one byte of data is available to be read\r
2d52a3a2 A	281	@retval FALSE No data is available to be read\r
051e63bb	282	\r
	283	**/\r
	284	BOOLEAN\r
	285	EFIAPI\r
	286	PL011UartPoll (\r
	287	IN UINTN UartBase\r
	288	);\r
	289	\r
	290	#endif\r