[mirror_edk2.git] / ArmPlatformPkg / Include / Drivers / PL341Dmc.h

/** @file\r
*\r
*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
*\r
*  This program and the accompanying materials\r
*  are licensed and made available under the terms and conditions of the BSD License\r
*  which accompanies this distribution.  The full text of the license may be found at\r
*  http://opensource.org/licenses/bsd-license.php\r
*\r
*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
*\r
**/\r
\r
#ifndef _PL341DMC_H_\r
#define _PL341DMC_H_\r
\r
\r
typedef struct  {\r
    UINTN	HasQos;        // has QoS registers\r
    UINTN	MaxChip;       // number of memory chips accessible\r
    BOOLEAN  IsUserCfg;\r
    UINT32  User0Cfg;\r
    UINT32  User2Cfg;\r
    UINT32	RefreshPeriod;\r
    UINT32	CasLatency;\r
    UINT32	WriteLatency;\r
    UINT32	t_mrd;\r
    UINT32	t_ras;\r
    UINT32	t_rc;\r
    UINT32	t_rcd;\r
    UINT32	t_rfc;\r
    UINT32	t_rp;\r
    UINT32	t_rrd;\r
    UINT32	t_wr;\r
    UINT32	t_wtr;\r
    UINT32	t_xp;\r
    UINT32	t_xsr;\r
    UINT32	t_esr;\r
    UINT32	MemoryCfg;\r
    UINT32	MemoryCfg2;\r
    UINT32	MemoryCfg3;\r
    UINT32	ChipCfg0;\r
    UINT32	ChipCfg1;\r
    UINT32	ChipCfg2;\r
    UINT32	ChipCfg3;\r
    UINT32	t_faw;\r
    UINT32	t_data_en;\r
    UINT32	t_wdata_en;\r
    UINT32  ModeReg;\r
    UINT32  ExtModeReg;\r
} PL341_DMC_CONFIG;\r
\r
/* Memory config bit fields */\r
#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_9      0x1\r
#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10     0x2\r
#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_11     0x3\r
#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_12     0x4\r
#define DMC_MEMORY_CONFIG_ROW_ADDRESS_11        (0x0 << 3)\r
#define DMC_MEMORY_CONFIG_ROW_ADDRESS_12        (0x1 << 3)\r
#define DMC_MEMORY_CONFIG_ROW_ADDRESS_13        (0x2 << 3)\r
#define DMC_MEMORY_CONFIG_ROW_ADDRESS_14        (0x3 << 3)\r
#define DMC_MEMORY_CONFIG_ROW_ADDRESS_15        (0x4 << 3)\r
#define DMC_MEMORY_CONFIG_ROW_ADDRESS_16        (0x5 << 3)\r
#define DMC_MEMORY_CONFIG_BURST_2               (0x1 << 15)\r
#define DMC_MEMORY_CONFIG_BURST_4               (0x2 << 15)\r
#define DMC_MEMORY_CONFIG_BURST_8               (0x3 << 15)\r
#define DMC_MEMORY_CONFIG_BURST_16              (0x4 << 15)\r
#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_1    (0x0 << 21)\r
#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_2    (0x1 << 21)\r
#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_3    (0x2 << 21)\r
#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_4    (0x3 << 21)\r
\r
#define DMC_MEMORY_CFG2_CLK_ASYNC    (0x0 << 0)\r
#define DMC_MEMORY_CFG2_CLK_SYNC    (0x1 << 0)\r
#define DMC_MEMORY_CFG2_DQM_INIT    (0x1 << 2)\r
#define DMC_MEMORY_CFG2_CKE_INIT    (0x1 << 3)\r
#define DMC_MEMORY_CFG2_BANK_BITS_2    (0x0 << 4)\r
#define DMC_MEMORY_CFG2_BANK_BITS_3    (0x3 << 4)\r
#define DMC_MEMORY_CFG2_MEM_WIDTH_16    (0x0 << 6)\r
#define DMC_MEMORY_CFG2_MEM_WIDTH_32    (0x1 << 6)\r
#define DMC_MEMORY_CFG2_MEM_WIDTH_64    (0x2 << 6)\r
#define DMC_MEMORY_CFG2_MEM_WIDTH_RESERVED  (0x3 << 6)\r
\r
//\r
// DMC Configuration Register Map\r
//\r
#define DMC_STATUS_REG              0x00\r
#define DMC_COMMAND_REG             0x04\r
#define DMC_DIRECT_CMD_REG          0x08\r
#define DMC_MEMORY_CONFIG_REG       0x0C\r
#define DMC_REFRESH_PRD_REG         0x10\r
#define DMC_CAS_LATENCY_REG         0x14\r
#define DMC_WRITE_LATENCY_REG       0x18\r
#define DMC_T_MRD_REG               0x1C\r
#define DMC_T_RAS_REG               0x20\r
#define DMC_T_RC_REG                0x24\r
#define DMC_T_RCD_REG               0x28\r
#define DMC_T_RFC_REG               0x2C\r
#define DMC_T_RP_REG                0x30\r
#define DMC_T_RRD_REG               0x34\r
#define DMC_T_WR_REG                0x38\r
#define DMC_T_WTR_REG               0x3C\r
#define DMC_T_XP_REG                0x40\r
#define DMC_T_XSR_REG               0x44\r
#define DMC_T_ESR_REG               0x48\r
#define DMC_MEMORY_CFG2_REG         0x4C\r
#define DMC_MEMORY_CFG3_REG         0x50\r
#define DMC_T_FAW_REG               0x54\r
#define DMC_T_RDATA_EN              0x5C	/* DFI read data enable register */\r
#define DMC_T_WRLAT_DIFF            0x60        /* DFI write data enable register */\r
\r
// Returns the state of the memory controller:\r
#define DMC_STATUS_CONFIG       0x0\r
#define DMC_STATUS_READY        0x1\r
#define DMC_STATUS_PAUSED       0x2\r
#define DMC_STATUS_LOWPOWER     0x3\r
\r
// Changes the state of the memory controller:\r
#define DMC_COMMAND_GO              0x0\r
#define DMC_COMMAND_SLEEP           0x1\r
#define DMC_COMMAND_WAKEUP          0x2\r
#define DMC_COMMAND_PAUSE           0x3\r
#define DMC_COMMAND_CONFIGURE       0x4\r
#define DMC_COMMAND_ACTIVEPAUSE     0x7\r
\r
// Determines the command required\r
#define DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL      0x0\r
#define DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH       (0x1 << 18)\r
#define DMC_DIRECT_CMD_MEMCMD_MODEREG           (0x2 << 18)\r
#define DMC_DIRECT_CMD_MEMCMD_EXTMODEREG        (0x2 << 18)\r
#define DMC_DIRECT_CMD_MEMCMD_NOP               (0x3 << 18)\r
#define DMC_DIRECT_CMD_MEMCMD_DPD               (0x1 << 22)\r
#define DMC_DIRECT_CMD_BANKADDR(n)              ((n & 0x3) << 16)\r
#define DMC_DIRECT_CMD_CHIP_ADDR(n)             ((n & 0x3) << 20)\r
\r
\r
//\r
// AXI ID configuration register map\r
//\r
#define DMC_ID_0_CFG_REG            0x100\r
#define DMC_ID_1_CFG_REG            0x104\r
#define DMC_ID_2_CFG_REG            0x108\r
#define DMC_ID_3_CFG_REG            0x10C\r
#define DMC_ID_4_CFG_REG            0x110\r
#define DMC_ID_5_CFG_REG            0x114\r
#define DMC_ID_6_CFG_REG            0x118\r
#define DMC_ID_7_CFG_REG            0x11C\r
#define DMC_ID_8_CFG_REG            0x120\r
#define DMC_ID_9_CFG_REG            0x124\r
#define DMC_ID_10_CFG_REG           0x128\r
#define DMC_ID_11_CFG_REG           0x12C\r
#define DMC_ID_12_CFG_REG           0x130\r
#define DMC_ID_13_CFG_REG           0x134\r
#define DMC_ID_14_CFG_REG           0x138\r
#define DMC_ID_15_CFG_REG           0x13C\r
\r
// Set the QoS\r
#define DMC_ID_CFG_QOS_DISABLE      0\r
#define DMC_ID_CFG_QOS_ENABLE       1\r
#define DMC_ID_CFG_QOS_MIN          2\r
\r
\r
//\r
// Chip configuration register map\r
//\r
#define DMC_CHIP_0_CFG_REG          0x200\r
#define DMC_CHIP_1_CFG_REG          0x204\r
#define DMC_CHIP_2_CFG_REG          0x208\r
#define DMC_CHIP_3_CFG_REG          0x20C\r
\r
//\r
// User Defined Pins\r
//\r
#define DMC_USER_STATUS_REG         0x300\r
#define DMC_USER_0_CFG_REG          0x304\r
#define DMC_USER_1_CFG_REG          0x308\r
#define DMC_FEATURE_CRTL_REG        0x30C\r
#define DMC_USER_2_CFG_REG          0x310\r
\r
\r
//\r
// PHY Register Settings\r
//\r
#define PHY_PTM_DFI_CLK_RANGE					0xE00		// DDR2 PHY PTM register offset\r
#define PHY_PTM_IOTERM							0xE04\r
#define PHY_PTM_PLL_EN          				0xe0c\r
#define PHY_PTM_PLL_RANGE       				0xe18\r
#define PHY_PTM_FEEBACK_DIV     				0xe1c\r
#define PHY_PTM_RCLK_DIV        				0xe20\r
#define PHY_PTM_LOCK_STATUS     				0xe28\r
#define PHY_PTM_INIT_DONE	     				0xe34\r
#define PHY_PTM_ADDCOM_IOSTR_OFF				0xec8\r
#define PHY_PTM_SQU_TRAINING    				0xee8\r
#define PHY_PTM_SQU_STAT        				0xeec\r
\r
// ==============================================================================\r
// PIPD 40G DDR2/DDR3 PHY Register definitions\r
//\r
// Offsets from APB Base Address\r
// ==============================================================================\r
#define PHY_BYTE0_OFFSET					0x000\r
#define PHY_BYTE1_OFFSET					0x200\r
#define PHY_BYTE2_OFFSET					0x400\r
#define PHY_BYTE3_OFFSET					0x600\r
\r
#define PHY_BYTE0_COARSE_SQADJ_INIT			0x064	;// Coarse squelch adjust\r
#define PHY_BYTE1_COARSE_SQADJ_INIT			0x264	;// Coarse squelch adjust\r
#define PHY_BYTE2_COARSE_SQADJ_INIT			0x464	;// Coarse squelch adjust\r
#define PHY_BYTE3_COARSE_SQADJ_INIT			0x664	;// Coarse squelch adjust\r
\r
#define PHY_BYTE0_IOSTR_OFFSET				0x004\r
#define PHY_BYTE1_IOSTR_OFFSET				0x204\r
#define PHY_BYTE2_IOSTR_OFFSET				0x404\r
#define PHY_BYTE3_IOSTR_OFFSET				0x604\r
\r
\r
;//--------------------------------------------------------------------------\r
\r
// DFI Clock ranges:\r
\r
#define PHY_PTM_DFI_CLK_RANGE_200MHz   		0x0\r
#define PHY_PTM_DFI_CLK_RANGE_201_267MHz	0x1\r
#define PHY_PTM_DFI_CLK_RANGE_268_333MHz	0x2\r
#define PHY_PTM_DFI_CLK_RANGE_334_400MHz	0x3\r
#define PHY_PTM_DFI_CLK_RANGE_401_533MHz	0x4\r
#define PHY_PTM_DFI_CLK_RANGE_534_667MHz	0x5\r
#define PHY_PTM_DFI_CLK_RANGE_668_800MHz	0x6\r
\r
\r
\r
#define  PHY_PTM_DFI_CLK_RANGE_VAL			PHY_PTM_DFI_CLK_RANGE_334_400MHz\r
\r
//--------------------------------------------------------------------------\r
\r
\r
// PLL Range\r
\r
#define PHY_PTM_PLL_RANGE_200_400MHz		0x0	// b0 = frequency >= 200 MHz and < 400 MHz\r
#define PHY_PTM_PLL_RANGE_400_800MHz		0x1	// b1 = frequency >= 400 MHz.\r
#define PHY_PTM_FEEBACK_DIV_200_400MHz		0x0	// b0 = frequency >= 200 MHz and < 400 MHz\r
#define PHY_PTM_FEEBACK_DIV_400_800MHz		0x1	// b1 = frequency >= 400 MHz.\r
#define PHY_PTM_REFCLK_DIV_200_400MHz		0x0\r
#define PHY_PTM_REFCLK_DIV_400_800MHz		0x1\r
\r
#define TC_UIOLHNC_MASK                         0x000003C0\r
#define TC_UIOLHNC_SHIFT                        0x6\r
#define TC_UIOLHPC_MASK                         0x0000003F\r
#define TC_UIOLHPC_SHIFT                        0x2\r
#define TC_UIOHOCT_MASK                         0x2\r
#define TC_UIOHOCT_SHIFT                        0x1\r
#define TC_UIOHSTOP_SHIFT                       0x0\r
#define TC_UIOLHXC_VALUE                        0x4\r
\r
#define PHY_PTM_SQU_TRAINING_ENABLE				0x1\r
#define PHY_PTM_SQU_TRAINING_DISABLE				0x0\r
\r
\r
//--------------------------------------\r
// JEDEC DDR2 Device Register definitions and settings\r
//--------------------------------------\r
#define DDR_MODESET_SHFT						14\r
#define DDR_MODESET_MR							0x0		;// Mode register\r
#define DDR_MODESET_EMR							0x1		;// Extended Mode register\r
#define DDR_MODESET_EMR2						0x2\r
#define DDR_MODESET_EMR3						0x3\r
\r
//\r
// Extended Mode Register settings\r
//\r
#define DDR_EMR_OCD_MASK                        0x0000380\r
#define DDR_EMR_OCD_SHIFT                       0x7\r
#define DDR_EMR_RTT_MASK                        0x00000044                  // DDR2 Device RTT (ODT) settings\r
#define DDR_EMR_RTT_SHIFT                       0x2\r
#define DDR_EMR_ODS_MASK                        0x00000002                  // DDR2 Output Drive Strength\r
#define DDR_EMR_ODS_SHIFT                       0x0001\r
\r
// Termination Values:\r
#define DDR_EMR_RTT_50R                         0x00000044                  // DDR2 50 Ohm termination\r
#define DDR_EMR_RTT_75R                         0x00000004                  // DDR2 75 Ohm termination\r
#define DDR_EMR_RTT_150                         0x00000040                  // DDR2 150 Ohm termination\r
\r
// Output Drive Strength Values:\r
#define DDR_EMR_ODS_FULL                        0x0                         // DDR2 Full Drive Strength\r
#define DDR_EMR_ODS_HALF                        0x1                         // DDR2 Half Drive Strength\r
\r
// OCD values\r
#define DDR_EMR_OCD_DEFAULT                     0x7\r
#define DDR_EMR_OCD_NS                          0x0\r
\r
#define DDR_EMR_ODS_VAL                         DDR_EMR_ODS_FULL\r
\r
#define DDR_SDRAM_START_ADDR					0x10000000\r
\r
\r
// ----------------------------------------\r
// PHY IOTERM values\r
// ----------------------------------------\r
#define PHY_PTM_IOTERM_OFF					0x0\r
#define PHY_PTM_IOTERM_150R					0x1\r
#define PHY_PTM_IOTERM_75R					0x2\r
#define PHY_PTM_IOTERM_50R					0x3\r
\r
#define PHY_BYTE_IOSTR_60OHM				0x0\r
#define PHY_BYTE_IOSTR_40OHM				0x1\r
#define PHY_BYTE_IOSTR_30OHM				0x2\r
#define PHY_BYTE_IOSTR_30AOHM				0x3\r
\r
#define DDR2_MR_BURST_LENGTH_4     (2)\r
#define DDR2_MR_BURST_LENGTH_8     (3)\r
#define DDR2_MR_DLL_RESET          (1 << 8)\r
#define DDR2_MR_CAS_LATENCY_4      (4 << 4)\r
#define DDR2_MR_CAS_LATENCY_5      (5 << 4)\r
#define DDR2_MR_CAS_LATENCY_6      (6 << 4)\r
#define DDR2_MR_WR_CYCLES_2        (1 << 9)\r
#define DDR2_MR_WR_CYCLES_3        (2 << 9)\r
#define DDR2_MR_WR_CYCLES_4        (3 << 9)\r
#define DDR2_MR_WR_CYCLES_5        (4 << 9)\r
#define DDR2_MR_WR_CYCLES_6        (5 << 9)\r
\r
\r
VOID\r
PL341DmcInit (\r
  IN  UINTN             DmcBase,\r
  IN  PL341_DMC_CONFIG* DmcConfig\r
  );\r
\r
VOID PL341DmcPhyInit (\r
  IN UINTN   DmcPhyBase\r
  );\r
\r
VOID PL341DmcTrainPHY (\r
  IN UINTN   DmcPhyBase\r
  );\r
\r
#endif /* _PL341DMC_H_ */\r
Commit	Line	Data
1e57a462	1	/** @file\r
	2	*\r
	3	* Copyright (c) 2011, ARM Limited. All rights reserved.\r
	4	*\r
	5	* This program and the accompanying materials\r
	6	* are licensed and made available under the terms and conditions of the BSD License\r
	7	* which accompanies this distribution. The full text of the license may be found at\r
	8	* http://opensource.org/licenses/bsd-license.php\r
	9	*\r
	10	* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	12	*\r
	13	**/\r
	14	\r
	15	#ifndef _PL341DMC_H_\r
	16	#define _PL341DMC_H_\r
	17	\r
	18	\r
	19	typedef struct {\r
	20	UINTN HasQos; // has QoS registers\r
	21	UINTN MaxChip; // number of memory chips accessible\r
	22	BOOLEAN IsUserCfg;\r
	23	UINT32 User0Cfg;\r
	24	UINT32 User2Cfg;\r
	25	UINT32 RefreshPeriod;\r
	26	UINT32 CasLatency;\r
	27	UINT32 WriteLatency;\r
	28	UINT32 t_mrd;\r
	29	UINT32 t_ras;\r
	30	UINT32 t_rc;\r
	31	UINT32 t_rcd;\r
	32	UINT32 t_rfc;\r
	33	UINT32 t_rp;\r
	34	UINT32 t_rrd;\r
	35	UINT32 t_wr;\r
	36	UINT32 t_wtr;\r
	37	UINT32 t_xp;\r
	38	UINT32 t_xsr;\r
	39	UINT32 t_esr;\r
	40	UINT32 MemoryCfg;\r
	41	UINT32 MemoryCfg2;\r
	42	UINT32 MemoryCfg3;\r
	43	UINT32 ChipCfg0;\r
	44	UINT32 ChipCfg1;\r
	45	UINT32 ChipCfg2;\r
	46	UINT32 ChipCfg3;\r
	47	UINT32 t_faw;\r
	48	UINT32 t_data_en;\r
	49	UINT32 t_wdata_en;\r
	50	UINT32 ModeReg;\r
	51	UINT32 ExtModeReg;\r
	52	} PL341_DMC_CONFIG;\r
	53	\r
	54	/* Memory config bit fields */\r
	55	#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_9 0x1\r
	56	#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10 0x2\r
	57	#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_11 0x3\r
	58	#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_12 0x4\r
	59	#define DMC_MEMORY_CONFIG_ROW_ADDRESS_11 (0x0 << 3)\r
	60	#define DMC_MEMORY_CONFIG_ROW_ADDRESS_12 (0x1 << 3)\r
	61	#define DMC_MEMORY_CONFIG_ROW_ADDRESS_13 (0x2 << 3)\r
	62	#define DMC_MEMORY_CONFIG_ROW_ADDRESS_14 (0x3 << 3)\r
	63	#define DMC_MEMORY_CONFIG_ROW_ADDRESS_15 (0x4 << 3)\r
	64	#define DMC_MEMORY_CONFIG_ROW_ADDRESS_16 (0x5 << 3)\r
65	#define DMC_MEMORY_CONFIG_BURST_2 (0x1 << 15)\r
66	#define DMC_MEMORY_CONFIG_BURST_4 (0x2 << 15)\r
67	#define DMC_MEMORY_CONFIG_BURST_8 (0x3 << 15)\r
68	#define DMC_MEMORY_CONFIG_BURST_16 (0x4 << 15)\r
69	#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_1 (0x0 << 21)\r
70	#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_2 (0x1 << 21)\r
71	#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_3 (0x2 << 21)\r
72	#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_4 (0x3 << 21)\r
73	\r
74	#define DMC_MEMORY_CFG2_CLK_ASYNC (0x0 << 0)\r
75	#define DMC_MEMORY_CFG2_CLK_SYNC (0x1 << 0)\r
76	#define DMC_MEMORY_CFG2_DQM_INIT (0x1 << 2)\r
77	#define DMC_MEMORY_CFG2_CKE_INIT (0x1 << 3)\r
78	#define DMC_MEMORY_CFG2_BANK_BITS_2 (0x0 << 4)\r
79	#define DMC_MEMORY_CFG2_BANK_BITS_3 (0x3 << 4)\r
80	#define DMC_MEMORY_CFG2_MEM_WIDTH_16 (0x0 << 6)\r
81	#define DMC_MEMORY_CFG2_MEM_WIDTH_32 (0x1 << 6)\r
82	#define DMC_MEMORY_CFG2_MEM_WIDTH_64 (0x2 << 6)\r
83	#define DMC_MEMORY_CFG2_MEM_WIDTH_RESERVED (0x3 << 6)\r
84	\r
85	//\r
86	// DMC Configuration Register Map\r
87	//\r
88	#define DMC_STATUS_REG 0x00\r
89	#define DMC_COMMAND_REG 0x04\r
90	#define DMC_DIRECT_CMD_REG 0x08\r
91	#define DMC_MEMORY_CONFIG_REG 0x0C\r
92	#define DMC_REFRESH_PRD_REG 0x10\r
93	#define DMC_CAS_LATENCY_REG 0x14\r
94	#define DMC_WRITE_LATENCY_REG 0x18\r
95	#define DMC_T_MRD_REG 0x1C\r
96	#define DMC_T_RAS_REG 0x20\r
97	#define DMC_T_RC_REG 0x24\r
98	#define DMC_T_RCD_REG 0x28\r
99	#define DMC_T_RFC_REG 0x2C\r
100	#define DMC_T_RP_REG 0x30\r
101	#define DMC_T_RRD_REG 0x34\r
102	#define DMC_T_WR_REG 0x38\r
103	#define DMC_T_WTR_REG 0x3C\r
104	#define DMC_T_XP_REG 0x40\r
105	#define DMC_T_XSR_REG 0x44\r
106	#define DMC_T_ESR_REG 0x48\r
107	#define DMC_MEMORY_CFG2_REG 0x4C\r
108	#define DMC_MEMORY_CFG3_REG 0x50\r
109	#define DMC_T_FAW_REG 0x54\r
110	#define DMC_T_RDATA_EN 0x5C /* DFI read data enable register */\r
111	#define DMC_T_WRLAT_DIFF 0x60 /* DFI write data enable register */\r
112	\r
113	// Returns the state of the memory controller:\r
114	#define DMC_STATUS_CONFIG 0x0\r
115	#define DMC_STATUS_READY 0x1\r
116	#define DMC_STATUS_PAUSED 0x2\r
117	#define DMC_STATUS_LOWPOWER 0x3\r
118	\r
119	// Changes the state of the memory controller:\r
120	#define DMC_COMMAND_GO 0x0\r
121	#define DMC_COMMAND_SLEEP 0x1\r
122	#define DMC_COMMAND_WAKEUP 0x2\r
123	#define DMC_COMMAND_PAUSE 0x3\r
124	#define DMC_COMMAND_CONFIGURE 0x4\r
125	#define DMC_COMMAND_ACTIVEPAUSE 0x7\r
126	\r
127	// Determines the command required\r
128	#define DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL 0x0\r
129	#define DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH (0x1 << 18)\r
130	#define DMC_DIRECT_CMD_MEMCMD_MODEREG (0x2 << 18)\r
131	#define DMC_DIRECT_CMD_MEMCMD_EXTMODEREG (0x2 << 18)\r
132	#define DMC_DIRECT_CMD_MEMCMD_NOP (0x3 << 18)\r
133	#define DMC_DIRECT_CMD_MEMCMD_DPD (0x1 << 22)\r
134	#define DMC_DIRECT_CMD_BANKADDR(n) ((n & 0x3) << 16)\r
135	#define DMC_DIRECT_CMD_CHIP_ADDR(n) ((n & 0x3) << 20)\r
136	\r
137	\r
138	//\r
139	// AXI ID configuration register map\r
140	//\r
141	#define DMC_ID_0_CFG_REG 0x100\r
142	#define DMC_ID_1_CFG_REG 0x104\r
143	#define DMC_ID_2_CFG_REG 0x108\r
144	#define DMC_ID_3_CFG_REG 0x10C\r
145	#define DMC_ID_4_CFG_REG 0x110\r
146	#define DMC_ID_5_CFG_REG 0x114\r
147	#define DMC_ID_6_CFG_REG 0x118\r
148	#define DMC_ID_7_CFG_REG 0x11C\r
149	#define DMC_ID_8_CFG_REG 0x120\r
150	#define DMC_ID_9_CFG_REG 0x124\r
151	#define DMC_ID_10_CFG_REG 0x128\r
152	#define DMC_ID_11_CFG_REG 0x12C\r
153	#define DMC_ID_12_CFG_REG 0x130\r
154	#define DMC_ID_13_CFG_REG 0x134\r
155	#define DMC_ID_14_CFG_REG 0x138\r
156	#define DMC_ID_15_CFG_REG 0x13C\r
157	\r
158	// Set the QoS\r
159	#define DMC_ID_CFG_QOS_DISABLE 0\r
160	#define DMC_ID_CFG_QOS_ENABLE 1\r
161	#define DMC_ID_CFG_QOS_MIN 2\r
162	\r
163	\r
164	//\r
165	// Chip configuration register map\r
166	//\r
167	#define DMC_CHIP_0_CFG_REG 0x200\r
168	#define DMC_CHIP_1_CFG_REG 0x204\r
169	#define DMC_CHIP_2_CFG_REG 0x208\r
170	#define DMC_CHIP_3_CFG_REG 0x20C\r
171	\r
172	//\r
173	// User Defined Pins\r
174	//\r
175	#define DMC_USER_STATUS_REG 0x300\r
176	#define DMC_USER_0_CFG_REG 0x304\r
177	#define DMC_USER_1_CFG_REG 0x308\r
178	#define DMC_FEATURE_CRTL_REG 0x30C\r
179	#define DMC_USER_2_CFG_REG 0x310\r
180	\r
181	\r
182	//\r
183	// PHY Register Settings\r
184	//\r
185	#define PHY_PTM_DFI_CLK_RANGE 0xE00 // DDR2 PHY PTM register offset\r
186	#define PHY_PTM_IOTERM 0xE04\r
187	#define PHY_PTM_PLL_EN 0xe0c\r
188	#define PHY_PTM_PLL_RANGE 0xe18\r
189	#define PHY_PTM_FEEBACK_DIV 0xe1c\r
190	#define PHY_PTM_RCLK_DIV 0xe20\r
191	#define PHY_PTM_LOCK_STATUS 0xe28\r
192	#define PHY_PTM_INIT_DONE 0xe34\r
193	#define PHY_PTM_ADDCOM_IOSTR_OFF 0xec8\r
194	#define PHY_PTM_SQU_TRAINING 0xee8\r
195	#define PHY_PTM_SQU_STAT 0xeec\r
196	\r
197	// ==============================================================================\r
198	// PIPD 40G DDR2/DDR3 PHY Register definitions\r
199	//\r
200	// Offsets from APB Base Address\r
201	// ==============================================================================\r
202	#define PHY_BYTE0_OFFSET 0x000\r
203	#define PHY_BYTE1_OFFSET 0x200\r
204	#define PHY_BYTE2_OFFSET 0x400\r
205	#define PHY_BYTE3_OFFSET 0x600\r
206	\r
207	#define PHY_BYTE0_COARSE_SQADJ_INIT 0x064 ;// Coarse squelch adjust\r
208	#define PHY_BYTE1_COARSE_SQADJ_INIT 0x264 ;// Coarse squelch adjust\r
209	#define PHY_BYTE2_COARSE_SQADJ_INIT 0x464 ;// Coarse squelch adjust\r
210	#define PHY_BYTE3_COARSE_SQADJ_INIT 0x664 ;// Coarse squelch adjust\r
211	\r
212	#define PHY_BYTE0_IOSTR_OFFSET 0x004\r
213	#define PHY_BYTE1_IOSTR_OFFSET 0x204\r
214	#define PHY_BYTE2_IOSTR_OFFSET 0x404\r
215	#define PHY_BYTE3_IOSTR_OFFSET 0x604\r
216	\r
217	\r
218	;//--------------------------------------------------------------------------\r
219	\r
220	// DFI Clock ranges:\r
221	\r
222	#define PHY_PTM_DFI_CLK_RANGE_200MHz 0x0\r
223	#define PHY_PTM_DFI_CLK_RANGE_201_267MHz 0x1\r
224	#define PHY_PTM_DFI_CLK_RANGE_268_333MHz 0x2\r
225	#define PHY_PTM_DFI_CLK_RANGE_334_400MHz 0x3\r
226	#define PHY_PTM_DFI_CLK_RANGE_401_533MHz 0x4\r
227	#define PHY_PTM_DFI_CLK_RANGE_534_667MHz 0x5\r
228	#define PHY_PTM_DFI_CLK_RANGE_668_800MHz 0x6\r
229	\r
230	\r
231	\r
232	#define PHY_PTM_DFI_CLK_RANGE_VAL PHY_PTM_DFI_CLK_RANGE_334_400MHz\r
233	\r
234	//--------------------------------------------------------------------------\r
235	\r
236	\r
237	// PLL Range\r
238	\r
239	#define PHY_PTM_PLL_RANGE_200_400MHz 0x0 // b0 = frequency >= 200 MHz and < 400 MHz\r
240	#define PHY_PTM_PLL_RANGE_400_800MHz 0x1 // b1 = frequency >= 400 MHz.\r
241	#define PHY_PTM_FEEBACK_DIV_200_400MHz 0x0 // b0 = frequency >= 200 MHz and < 400 MHz\r
242	#define PHY_PTM_FEEBACK_DIV_400_800MHz 0x1 // b1 = frequency >= 400 MHz.\r
243	#define PHY_PTM_REFCLK_DIV_200_400MHz 0x0\r
244	#define PHY_PTM_REFCLK_DIV_400_800MHz 0x1\r
245	\r
246	#define TC_UIOLHNC_MASK 0x000003C0\r
247	#define TC_UIOLHNC_SHIFT 0x6\r
248	#define TC_UIOLHPC_MASK 0x0000003F\r
249	#define TC_UIOLHPC_SHIFT 0x2\r
250	#define TC_UIOHOCT_MASK 0x2\r
251	#define TC_UIOHOCT_SHIFT 0x1\r
252	#define TC_UIOHSTOP_SHIFT 0x0\r
253	#define TC_UIOLHXC_VALUE 0x4\r
254	\r
255	#define PHY_PTM_SQU_TRAINING_ENABLE 0x1\r
256	#define PHY_PTM_SQU_TRAINING_DISABLE 0x0\r
257	\r
258	\r
259	//--------------------------------------\r
260	// JEDEC DDR2 Device Register definitions and settings\r
261	//--------------------------------------\r
262	#define DDR_MODESET_SHFT 14\r
263	#define DDR_MODESET_MR 0x0 ;// Mode register\r
264	#define DDR_MODESET_EMR 0x1 ;// Extended Mode register\r
265	#define DDR_MODESET_EMR2 0x2\r
266	#define DDR_MODESET_EMR3 0x3\r
267	\r
268	//\r
269	// Extended Mode Register settings\r
270	//\r
271	#define DDR_EMR_OCD_MASK 0x0000380\r
272	#define DDR_EMR_OCD_SHIFT 0x7\r
273	#define DDR_EMR_RTT_MASK 0x00000044 // DDR2 Device RTT (ODT) settings\r
274	#define DDR_EMR_RTT_SHIFT 0x2\r
275	#define DDR_EMR_ODS_MASK 0x00000002 // DDR2 Output Drive Strength\r
276	#define DDR_EMR_ODS_SHIFT 0x0001\r
277	\r
278	// Termination Values:\r
279	#define DDR_EMR_RTT_50R 0x00000044 // DDR2 50 Ohm termination\r
280	#define DDR_EMR_RTT_75R 0x00000004 // DDR2 75 Ohm termination\r
281	#define DDR_EMR_RTT_150 0x00000040 // DDR2 150 Ohm termination\r
282	\r
283	// Output Drive Strength Values:\r
284	#define DDR_EMR_ODS_FULL 0x0 // DDR2 Full Drive Strength\r
285	#define DDR_EMR_ODS_HALF 0x1 // DDR2 Half Drive Strength\r
286	\r
287	// OCD values\r
288	#define DDR_EMR_OCD_DEFAULT 0x7\r
289	#define DDR_EMR_OCD_NS 0x0\r
290	\r
291	#define DDR_EMR_ODS_VAL DDR_EMR_ODS_FULL\r
292	\r
293	#define DDR_SDRAM_START_ADDR 0x10000000\r
294	\r
295	\r
296	// ----------------------------------------\r
297	// PHY IOTERM values\r
298	// ----------------------------------------\r
299	#define PHY_PTM_IOTERM_OFF 0x0\r
300	#define PHY_PTM_IOTERM_150R 0x1\r
301	#define PHY_PTM_IOTERM_75R 0x2\r
302	#define PHY_PTM_IOTERM_50R 0x3\r
303	\r
304	#define PHY_BYTE_IOSTR_60OHM 0x0\r
305	#define PHY_BYTE_IOSTR_40OHM 0x1\r
306	#define PHY_BYTE_IOSTR_30OHM 0x2\r
307	#define PHY_BYTE_IOSTR_30AOHM 0x3\r
308	\r
309	#define DDR2_MR_BURST_LENGTH_4 (2)\r
310	#define DDR2_MR_BURST_LENGTH_8 (3)\r
311	#define DDR2_MR_DLL_RESET (1 << 8)\r
312	#define DDR2_MR_CAS_LATENCY_4 (4 << 4)\r
313	#define DDR2_MR_CAS_LATENCY_5 (5 << 4)\r
314	#define DDR2_MR_CAS_LATENCY_6 (6 << 4)\r
315	#define DDR2_MR_WR_CYCLES_2 (1 << 9)\r
316	#define DDR2_MR_WR_CYCLES_3 (2 << 9)\r
317	#define DDR2_MR_WR_CYCLES_4 (3 << 9)\r
318	#define DDR2_MR_WR_CYCLES_5 (4 << 9)\r
319	#define DDR2_MR_WR_CYCLES_6 (5 << 9)\r
320	\r
321	\r
322	VOID\r
323	PL341DmcInit (\r
324	IN UINTN DmcBase,\r
325	IN PL341_DMC_CONFIG* DmcConfig\r
326	);\r
327	\r
328	VOID PL341DmcPhyInit (\r
329	IN UINTN DmcPhyBase\r
330	);\r
331	\r
332	VOID PL341DmcTrainPHY (\r
333	IN UINTN DmcPhyBase\r
334	);\r
335	\r
336	#endif /* _PL341DMC_H_ */\r