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1d5d0ae9 | 1 | /** @file\r |
2 | *\r | |
3 | * Copyright (c) 2011, ARM Limited. All rights reserved.\r | |
1d5d0ae9 | 4 | *\r |
3402aac7 RC |
5 | * This program and the accompanying materials\r |
6 | * are licensed and made available under the terms and conditions of the BSD License\r | |
7 | * which accompanies this distribution. The full text of the license may be found at\r | |
8 | * http://opensource.org/licenses/bsd-license.php\r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
1d5d0ae9 | 12 | *\r |
13 | **/\r | |
14 | \r | |
15 | \r | |
16 | #ifndef _SP804_TIMER_H__\r | |
17 | #define _SP804_TIMER_H__\r | |
18 | \r | |
19 | // SP804 Timer constants\r | |
cc1e8149 | 20 | // Note: The SP804 Timer module comprises two timers, Timer_0 and Timer_1\r |
21 | // These timers are identical and all their registers have an offset of 0x20\r | |
22 | // i.e. SP804_TIMER_0_LOAD_REG = 0x00 and SP804_TIMER_1_LOAD_REG = 0x20\r | |
23 | // Therefore, define all registers only once and adjust the base addresses by 0x20\r | |
24 | #define SP804_TIMER_LOAD_REG 0x00\r | |
25 | #define SP804_TIMER_CURRENT_REG 0x04\r | |
26 | #define SP804_TIMER_CONTROL_REG 0x08\r | |
27 | #define SP804_TIMER_INT_CLR_REG 0x0C\r | |
28 | #define SP804_TIMER_RAW_INT_STS_REG 0x10\r | |
29 | #define SP804_TIMER_MSK_INT_STS_REG 0x14\r | |
30 | #define SP804_TIMER_BG_LOAD_REG 0x18\r | |
1d5d0ae9 | 31 | \r |
32 | // Timer control register bit definitions\r | |
33 | #define SP804_TIMER_CTRL_ONESHOT BIT0\r | |
34 | #define SP804_TIMER_CTRL_32BIT BIT1\r | |
35 | #define SP804_TIMER_CTRL_PRESCALE_MASK (BIT3|BIT2)\r | |
36 | #define SP804_PRESCALE_DIV_1 0\r | |
37 | #define SP804_PRESCALE_DIV_16 BIT2\r | |
38 | #define SP804_PRESCALE_DIV_256 BIT3\r | |
39 | #define SP804_TIMER_CTRL_INT_ENABLE BIT5\r | |
40 | #define SP804_TIMER_CTRL_PERIODIC BIT6\r | |
41 | #define SP804_TIMER_CTRL_ENABLE BIT7\r | |
42 | \r | |
cc1e8149 | 43 | // Other SP804 Timer definitions\r |
44 | #define SP804_MAX_TICKS 0xFFFFFFFF\r | |
45 | \r | |
1d5d0ae9 | 46 | // SP810 System Controller constants\r |
47 | #define SP810_SYS_CTRL_REG 0x00\r | |
48 | #define SP810_SYS_CTRL_TIMER0_TIMCLK BIT15 // 0=REFCLK, 1=TIMCLK\r | |
49 | #define SP810_SYS_CTRL_TIMER0_EN BIT16\r | |
50 | #define SP810_SYS_CTRL_TIMER1_TIMCLK BIT17 // 0=REFCLK, 1=TIMCLK\r | |
51 | #define SP810_SYS_CTRL_TIMER1_EN BIT18\r | |
52 | #define SP810_SYS_CTRL_TIMER2_TIMCLK BIT19 // 0=REFCLK, 1=TIMCLK\r | |
53 | #define SP810_SYS_CTRL_TIMER2_EN BIT20\r | |
54 | #define SP810_SYS_CTRL_TIMER3_TIMCLK BIT21 // 0=REFCLK, 1=TIMCLK\r | |
55 | #define SP810_SYS_CTRL_TIMER3_EN BIT22\r | |
56 | \r | |
57 | #endif\r |