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1 | /** @file\r |
| 2 | *\r |
| 3 | * Copyright (c) 2011, ARM Limited. All rights reserved.\r |
| 4 | *\r |
| 5 | * This program and the accompanying materials\r |
| 6 | * are licensed and made available under the terms and conditions of the BSD License\r |
| 7 | * which accompanies this distribution. The full text of the license may be found at\r |
| 8 | * http://opensource.org/licenses/bsd-license.php\r |
| 9 | *\r |
| 10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| 12 | *\r |
| 13 | **/\r |
| 14 | \r |
| 15 | \r |
| 16 | #ifndef __SP805_WATCHDOG_H__\r |
| 17 | #define __SP805_WATCHDOG_H__\r |
| 18 | \r |
| 19 | #include <Base.h>\r |
| 20 | #include <ArmPlatform.h>\r |
| 21 | \r |
| 22 | // SP805 Watchdog Registers\r |
| 23 | #define SP805_WDOG_LOAD_REG (SP805_WDOG_BASE + 0x000)\r |
| 24 | #define SP805_WDOG_CURRENT_REG (SP805_WDOG_BASE + 0x004)\r |
| 25 | #define SP805_WDOG_CONTROL_REG (SP805_WDOG_BASE + 0x008)\r |
| 26 | #define SP805_WDOG_INT_CLR_REG (SP805_WDOG_BASE + 0x00C)\r |
| 27 | #define SP805_WDOG_RAW_INT_STS_REG (SP805_WDOG_BASE + 0x010)\r |
| 28 | #define SP805_WDOG_MSK_INT_STS_REG (SP805_WDOG_BASE + 0x014)\r |
| 29 | #define SP805_WDOG_LOCK_REG (SP805_WDOG_BASE + 0xC00)\r |
| 30 | \r |
| 31 | #define SP805_WDOG_PERIPH_ID0 (SP805_WDOG_BASE + 0xFE0)\r |
| 32 | #define SP805_WDOG_PERIPH_ID1 (SP805_WDOG_BASE + 0xFE4)\r |
| 33 | #define SP805_WDOG_PERIPH_ID2 (SP805_WDOG_BASE + 0xFE8)\r |
| 34 | #define SP805_WDOG_PERIPH_ID3 (SP805_WDOG_BASE + 0xFEC)\r |
| 35 | \r |
| 36 | #define SP805_WDOG_PCELL_ID0 (SP805_WDOG_BASE + 0xFF0)\r |
| 37 | #define SP805_WDOG_PCELL_ID1 (SP805_WDOG_BASE + 0xFF4)\r |
| 38 | #define SP805_WDOG_PCELL_ID2 (SP805_WDOG_BASE + 0xFF8)\r |
| 39 | #define SP805_WDOG_PCELL_ID3 (SP805_WDOG_BASE + 0xFFC)\r |
| 40 | \r |
| 41 | // Timer control register bit definitions\r |
| 42 | #define SP805_WDOG_CTRL_INTEN BIT0\r |
| 43 | #define SP805_WDOG_CTRL_RESEN BIT1\r |
| 44 | #define SP805_WDOG_RAW_INT_STS_WDOGRIS BIT0\r |
| 45 | #define SP805_WDOG_MSK_INT_STS_WDOGMIS BIT0\r |
| 46 | \r |
| 47 | #define SP805_WDOG_LOCK_IS_UNLOCKED 0x00000000\r |
| 48 | #define SP805_WDOG_LOCK_IS_LOCKED 0x00000001\r |
| 49 | #define SP805_WDOG_SPECIAL_UNLOCK_CODE 0x1ACCE551\r |
| 50 | \r |
| 51 | VOID\r |
| 52 | EFIAPI\r |
| 53 | ExitBootServicesEvent (\r |
| 54 | IN EFI_EVENT Event,\r |
| 55 | IN VOID *Context\r |
| 56 | );\r |
| 57 | \r |
| 58 | EFI_STATUS\r |
| 59 | EFIAPI\r |
| 60 | SP805SetTimerPeriod (\r |
| 61 | IN CONST EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,\r |
| 62 | IN UINT64 TimerPeriod // In 100ns units\r |
| 63 | );\r |
| 64 | \r |
| 65 | EFI_STATUS\r |
| 66 | EFIAPI\r |
| 67 | SP805GetTimerPeriod (\r |
| 68 | IN CONST EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,\r |
| 69 | OUT UINT64 *TimerPeriod\r |
| 70 | );\r |
| 71 | \r |
| 72 | EFI_STATUS\r |
| 73 | EFIAPI\r |
| 74 | SP805RegisterHandler (\r |
| 75 | IN CONST EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,\r |
| 76 | IN EFI_WATCHDOG_TIMER_NOTIFY NotifyFunction\r |
| 77 | );\r |
| 78 | \r |
| 79 | EFI_STATUS\r |
| 80 | SP805Initialize (\r |
| 81 | VOID\r |
| 82 | );\r |
| 83 | \r |
| 84 | EFI_STATUS\r |
| 85 | EFIAPI\r |
| 86 | SP805InstallProtocol (\r |
| 87 | IN EFI_HANDLE ImageHandle,\r |
| 88 | IN EFI_SYSTEM_TABLE *SystemTable\r |
| 89 | );\r |
| 90 | \r |
| 91 | \r |
| 92 | #endif // __SP805_WATCHDOG_H__\r |
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