[mirror_edk2.git] / ArmPlatformPkg / Include / Library / LcdPlatformLib.h

/** @file\r
\r
 Copyright (c) 2011-2018, ARM Ltd. All rights reserved.<BR>\r
 SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
 **/\r
\r
#ifndef LCD_PLATFORM_LIB_H_\r
#define LCD_PLATFORM_LIB_H_\r
\r
#include <Protocol/GraphicsOutput.h>\r
\r
#define LCD_VRAM_SIZE                     SIZE_8MB\r
\r
// Modes definitions\r
#define VGA                               0\r
#define SVGA                              1\r
#define XGA                               2\r
#define SXGA                              3\r
#define WSXGA                             4\r
#define UXGA                              5\r
#define HD                                6\r
#define WVGA                              7\r
#define QHD                               8\r
#define WSVGA                             9\r
#define HD720                             10\r
#define WXGA                              11\r
\r
// VGA Mode: 640 x 480\r
#define VGA_H_RES_PIXELS                  640\r
#define VGA_V_RES_PIXELS                  480\r
#define VGA_OSC_FREQUENCY                 23750000  /* 0x016A6570 */\r
\r
#define VGA_H_SYNC                        ( 80 - 1)\r
#define VGA_H_FRONT_PORCH                 ( 16 - 1)\r
#define VGA_H_BACK_PORCH                  ( 64 - 1)\r
\r
#define VGA_V_SYNC                        (  4 - 1)\r
#define VGA_V_FRONT_PORCH                 (  3 - 1)\r
#define VGA_V_BACK_PORCH                  ( 13 - 1)\r
\r
// SVGA Mode: 800 x 600\r
#define SVGA_H_RES_PIXELS                 800\r
#define SVGA_V_RES_PIXELS                 600\r
#define SVGA_OSC_FREQUENCY                38250000  /* 0x0247A610 */\r
\r
#define SVGA_H_SYNC                       ( 80 - 1)\r
#define SVGA_H_FRONT_PORCH                ( 32 - 1)\r
#define SVGA_H_BACK_PORCH                 (112 - 1)\r
\r
#define SVGA_V_SYNC                       (  4 - 1)\r
#define SVGA_V_FRONT_PORCH                (  3 - 1)\r
#define SVGA_V_BACK_PORCH                 ( 17 - 1)\r
\r
// XGA Mode: 1024 x 768\r
#define XGA_H_RES_PIXELS                  1024\r
#define XGA_V_RES_PIXELS                  768\r
#define XGA_OSC_FREQUENCY                 63500000  /* 0x03C8EEE0 */\r
\r
#define XGA_H_SYNC                        (104 - 1)\r
#define XGA_H_FRONT_PORCH                 ( 48 - 1)\r
#define XGA_H_BACK_PORCH                  (152 - 1)\r
\r
#define XGA_V_SYNC                        (  4 - 1)\r
#define XGA_V_FRONT_PORCH                 (  3 - 1)\r
#define XGA_V_BACK_PORCH                  ( 23 - 1)\r
\r
// SXGA Mode: 1280 x 1024\r
#define SXGA_H_RES_PIXELS                 1280\r
#define SXGA_V_RES_PIXELS                 1024\r
#define SXGA_OSC_FREQUENCY                109000000  /* 0x067F3540 */\r
\r
#define SXGA_H_SYNC                       (136 - 1)\r
#define SXGA_H_FRONT_PORCH                ( 80 - 1)\r
#define SXGA_H_BACK_PORCH                 (216 - 1)\r
\r
#define SXGA_V_SYNC                       (  7 - 1)\r
#define SXGA_V_FRONT_PORCH                (  3 - 1)\r
#define SXGA_V_BACK_PORCH                 ( 29 - 1)\r
\r
// WSXGA+ Mode: 1680 x 1050\r
#define WSXGA_H_RES_PIXELS                1680\r
#define WSXGA_V_RES_PIXELS                1050\r
#define WSXGA_OSC_FREQUENCY               147000000  /* 0x08C30AC0 */\r
\r
#define WSXGA_H_SYNC                      (170 - 1)\r
#define WSXGA_H_FRONT_PORCH               (104 - 1)\r
#define WSXGA_H_BACK_PORCH                (274 - 1)\r
\r
#define WSXGA_V_SYNC                      (  5 - 1)\r
#define WSXGA_V_FRONT_PORCH               (  4 - 1)\r
#define WSXGA_V_BACK_PORCH                ( 41 - 1)\r
\r
// UXGA Mode: 1600 x 1200\r
#define UXGA_H_RES_PIXELS                 1600\r
#define UXGA_V_RES_PIXELS                 1200\r
#define UXGA_OSC_FREQUENCY                161000000  /* 0x0998AA40 */\r
\r
#define UXGA_H_SYNC                       (168 - 1)\r
#define UXGA_H_FRONT_PORCH                (112 - 1)\r
#define UXGA_H_BACK_PORCH                 (280 - 1)\r
\r
#define UXGA_V_SYNC                       (  4 - 1)\r
#define UXGA_V_FRONT_PORCH                (  3 - 1)\r
#define UXGA_V_BACK_PORCH                 ( 38 - 1)\r
\r
// HD Mode: 1920 x 1080\r
#define HD_H_RES_PIXELS                   1920\r
#define HD_V_RES_PIXELS                   1080\r
#define HD_OSC_FREQUENCY                  165000000  /* 0x09D5B340 */\r
\r
#define HD_H_SYNC                         ( 79 - 1)\r
#define HD_H_FRONT_PORCH                  (128 - 1)\r
#define HD_H_BACK_PORCH                   (328 - 1)\r
\r
#define HD_V_SYNC                         (  5 - 1)\r
#define HD_V_FRONT_PORCH                  (  3 - 1)\r
#define HD_V_BACK_PORCH                   ( 32 - 1)\r
\r
// WVGA Mode: 800 x 480\r
#define WVGA_H_RES_PIXELS                 800\r
#define WVGA_V_RES_PIXELS                 480\r
#define WVGA_OSC_FREQUENCY                29500000   /* 0x01C22260 */\r
#define WVGA_H_SYNC                       ( 72 - 1)\r
#define WVGA_H_FRONT_PORCH                ( 24 - 1)\r
#define WVGA_H_BACK_PORCH                 ( 96 - 1)\r
#define WVGA_V_SYNC                       (  7 - 1)\r
#define WVGA_V_FRONT_PORCH                (  3 - 1)\r
#define WVGA_V_BACK_PORCH                 ( 10 - 1)\r
\r
// QHD Mode: 960 x 540\r
#define QHD_H_RES_PIXELS                  960\r
#define QHD_V_RES_PIXELS                  540\r
#define QHD_OSC_FREQUENCY                 40750000   /* 0x026DCBB0 */\r
#define QHD_H_SYNC                        ( 96 - 1)\r
#define QHD_H_FRONT_PORCH                 ( 32 - 1)\r
#define QHD_H_BACK_PORCH                  (128 - 1)\r
#define QHD_V_SYNC                        (  5 - 1)\r
#define QHD_V_FRONT_PORCH                 (  3 - 1)\r
#define QHD_V_BACK_PORCH                  ( 14 - 1)\r
\r
// WSVGA Mode: 1024 x 600\r
#define WSVGA_H_RES_PIXELS                1024\r
#define WSVGA_V_RES_PIXELS                600\r
#define WSVGA_OSC_FREQUENCY               49000000   /* 0x02EBAE40 */\r
#define WSVGA_H_SYNC                      (104 - 1)\r
#define WSVGA_H_FRONT_PORCH               ( 40 - 1)\r
#define WSVGA_H_BACK_PORCH                (144 - 1)\r
#define WSVGA_V_SYNC                      ( 10 - 1)\r
#define WSVGA_V_FRONT_PORCH               (  3 - 1)\r
#define WSVGA_V_BACK_PORCH                ( 11 - 1)\r
\r
// HD720 Mode: 1280 x 720\r
#define HD720_H_RES_PIXELS                 1280\r
#define HD720_V_RES_PIXELS                 720\r
#define HD720_OSC_FREQUENCY                74500000   /* 0x0470C7A0 */\r
#define HD720_H_SYNC                       (128 - 1)\r
#define HD720_H_FRONT_PORCH                ( 64 - 1)\r
#define HD720_H_BACK_PORCH                 (192 - 1)\r
#define HD720_V_SYNC                       (  5 - 1)\r
#define HD720_V_FRONT_PORCH                (  3 - 1)\r
#define HD720_V_BACK_PORCH                 ( 20 - 1)\r
\r
// WXGA Mode: 1280 x 800\r
#define WXGA_H_RES_PIXELS                  1280\r
#define WXGA_V_RES_PIXELS                  800\r
#define WXGA_OSC_FREQUENCY                 83500000  /* 0x04FA1BE0 */\r
#define WXGA_H_SYNC                        (128 - 1)\r
#define WXGA_H_FRONT_PORCH                 ( 72 - 1)\r
#define WXGA_H_BACK_PORCH                  (200 - 1)\r
#define WXGA_V_SYNC                        (  6 - 1)\r
#define WXGA_V_FRONT_PORCH                 (  3 - 1)\r
#define WXGA_V_BACK_PORCH                  ( 22 - 1)\r
\r
// Colour Masks\r
#define LCD_24BPP_RED_MASK              0x00FF0000\r
#define LCD_24BPP_GREEN_MASK            0x0000FF00\r
#define LCD_24BPP_BLUE_MASK             0x000000FF\r
#define LCD_24BPP_RESERVED_MASK         0xFF000000\r
\r
#define LCD_16BPP_555_RED_MASK          0x00007C00\r
#define LCD_16BPP_555_GREEN_MASK        0x000003E0\r
#define LCD_16BPP_555_BLUE_MASK         0x0000001F\r
#define LCD_16BPP_555_RESERVED_MASK     0x00000000\r
\r
#define LCD_16BPP_565_RED_MASK          0x0000F800\r
#define LCD_16BPP_565_GREEN_MASK        0x000007E0\r
#define LCD_16BPP_565_BLUE_MASK         0x0000001F\r
#define LCD_16BPP_565_RESERVED_MASK     0x00008000\r
\r
#define LCD_12BPP_444_RED_MASK          0x00000F00\r
#define LCD_12BPP_444_GREEN_MASK        0x000000F0\r
#define LCD_12BPP_444_BLUE_MASK         0x0000000F\r
#define LCD_12BPP_444_RESERVED_MASK     0x0000F000\r
\r
/** The enumeration maps the PL111 LcdBpp values used in the LCD Control\r
  Register\r
**/\r
typedef enum {\r
  LCD_BITS_PER_PIXEL_1 = 0,\r
  LCD_BITS_PER_PIXEL_2,\r
  LCD_BITS_PER_PIXEL_4,\r
  LCD_BITS_PER_PIXEL_8,\r
  LCD_BITS_PER_PIXEL_16_555,\r
  LCD_BITS_PER_PIXEL_24,\r
  LCD_BITS_PER_PIXEL_16_565,\r
  LCD_BITS_PER_PIXEL_12_444\r
} LCD_BPP;\r
\r
// Display timing settings.\r
typedef struct {\r
  UINT32                      Resolution;\r
  UINT32                      Sync;\r
  UINT32                      BackPorch;\r
  UINT32                      FrontPorch;\r
} SCAN_TIMINGS;\r
\r
/** Platform related initialization function.\r
\r
  @param[in] Handle              Handle to the LCD device instance.\r
\r
  @retval EFI_SUCCESS            Plaform library initialized successfully.\r
  @retval !(EFI_SUCCESS)         Other errors.\r
**/\r
EFI_STATUS\r
LcdPlatformInitializeDisplay (\r
  IN EFI_HANDLE   Handle\r
  );\r
\r
/** Allocate VRAM memory in DRAM for the framebuffer\r
  (unless it is reserved already).\r
\r
  The allocated address can be used to set the framebuffer.\r
\r
  @param[out] VramBaseAddress      A pointer to the framebuffer address.\r
  @param[out] VramSize             A pointer to the size of the frame\r
                                   buffer in bytes\r
\r
  @retval EFI_SUCCESS              Frame buffer memory allocated successfully.\r
  @retval !(EFI_SUCCESS)           Other errors.\r
**/\r
EFI_STATUS\r
LcdPlatformGetVram (\r
  OUT EFI_PHYSICAL_ADDRESS*                 VramBaseAddress,\r
  OUT UINTN*                                VramSize\r
  );\r
\r
/** Return total number of modes supported.\r
\r
  Note: Valid mode numbers are 0 to MaxMode - 1\r
  See Section 12.9 of the UEFI Specification 2.7\r
\r
  @retval UINT32             Mode Number.\r
**/\r
UINT32\r
LcdPlatformGetMaxMode (\r
  VOID\r
  );\r
\r
/** Set the requested display mode.\r
\r
  @param[in] ModeNumber            Mode Number.\r
\r
  @retval  EFI_SUCCESS             Mode set successfully.\r
  @retval  EFI_INVALID_PARAMETER   Requested mode not found.\r
  @retval  !(EFI_SUCCESS)          Other errors.\r
**/\r
EFI_STATUS\r
LcdPlatformSetMode (\r
  IN UINT32                                 ModeNumber\r
  );\r
\r
/** Return information for the requested mode number.\r
\r
  @param[in]  ModeNumber         Mode Number.\r
  @param[out] Info               Pointer for returned mode information\r
                                 (on success).\r
\r
  @retval EFI_SUCCESS             Mode information for the requested mode\r
                                  returned successfully.\r
  @retval EFI_INVALID_PARAMETER   Requested mode not found.\r
**/\r
EFI_STATUS\r
LcdPlatformQueryMode (\r
  IN  UINT32                                ModeNumber,\r
  OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION  *Info\r
  );\r
\r
/** Return display timing information for the requested mode number.\r
\r
  @param[in]  ModeNumber          Mode Number.\r
\r
  @param[out] Horizontal          Pointer to horizontal timing parameters.\r
                                  (Resolution, Sync, Back porch, Front porch)\r
  @param[out] Vertical            Pointer to vertical timing parameters.\r
                                  (Resolution, Sync, Back porch, Front porch)\r
\r
\r
  @retval EFI_SUCCESS             Display timing information for the requested\r
                                  mode returned successfully.\r
  @retval EFI_INVALID_PARAMETER   Requested mode not found.\r
**/\r
EFI_STATUS\r
LcdPlatformGetTimings (\r
  IN  UINT32                              ModeNumber,\r
  OUT SCAN_TIMINGS                        **Horizontal,\r
  OUT SCAN_TIMINGS                        **Vertical\r
  );\r
\r
/** Return bits per pixel information for a mode number.\r
\r
  @param[in]  ModeNumber          Mode Number.\r
\r
  @param[out] Bpp                 Pointer to value bits per pixel information.\r
\r
  @retval EFI_SUCCESS             Bit per pixel information for the requested\r
                                  mode returned successfully.\r
  @retval EFI_INVALID_PARAMETER   Requested mode not found.\r
**/\r
EFI_STATUS\r
LcdPlatformGetBpp (\r
  IN  UINT32                                ModeNumber,\r
  OUT LCD_BPP*                              Bpp\r
  );\r
\r
#endif /* LCD_PLATFORM_LIB_H_ */\r
Commit	Line	Data
7d0f2f23	1	/** @file\r
7d0f2f23	2	\r
b1b69d26	3	Copyright (c) 2011-2018, ARM Ltd. All rights reserved.<BR>\r
f4dfad05	4	SPDX-License-Identifier: BSD-2-Clause-Patent\r
7d0f2f23	5	\r
	6	**/\r
	7	\r
b1b69d26 GP	8	#ifndef LCD_PLATFORM_LIB_H_\r
b1b69d26 GP	9	#define LCD_PLATFORM_LIB_H_\r
7d0f2f23	10	\r
	11	#include <Protocol/GraphicsOutput.h>\r
	12	\r
	13	#define LCD_VRAM_SIZE SIZE_8MB\r
	14	\r
7d0f2f23	15	// Modes definitions\r
7d0f2f23	16	#define VGA 0\r
	17	#define SVGA 1\r
	18	#define XGA 2\r
	19	#define SXGA 3\r
beeb44f4	20	#define WSXGA 4\r
	21	#define UXGA 5\r
	22	#define HD 6\r
90347ab3 GP	23	#define WVGA 7\r
	24	#define QHD 8\r
	25	#define WSVGA 9\r
	26	#define HD720 10\r
	27	#define WXGA 11\r
7d0f2f23	28	\r
7d0f2f23	29	// VGA Mode: 640 x 480\r
7d0f2f23	30	#define VGA_H_RES_PIXELS 640\r
	31	#define VGA_V_RES_PIXELS 480\r
	32	#define VGA_OSC_FREQUENCY 23750000 /* 0x016A6570 */\r
	33	\r
	34	#define VGA_H_SYNC ( 80 - 1)\r
	35	#define VGA_H_FRONT_PORCH ( 16 - 1)\r
	36	#define VGA_H_BACK_PORCH ( 64 - 1)\r
	37	\r
	38	#define VGA_V_SYNC ( 4 - 1)\r
	39	#define VGA_V_FRONT_PORCH ( 3 - 1)\r
	40	#define VGA_V_BACK_PORCH ( 13 - 1)\r
	41	\r
7d0f2f23	42	// SVGA Mode: 800 x 600\r
7d0f2f23	43	#define SVGA_H_RES_PIXELS 800\r
	44	#define SVGA_V_RES_PIXELS 600\r
	45	#define SVGA_OSC_FREQUENCY 38250000 /* 0x0247A610 */\r
	46	\r
	47	#define SVGA_H_SYNC ( 80 - 1)\r
	48	#define SVGA_H_FRONT_PORCH ( 32 - 1)\r
	49	#define SVGA_H_BACK_PORCH (112 - 1)\r
	50	\r
	51	#define SVGA_V_SYNC ( 4 - 1)\r
	52	#define SVGA_V_FRONT_PORCH ( 3 - 1)\r
	53	#define SVGA_V_BACK_PORCH ( 17 - 1)\r
	54	\r
7d0f2f23	55	// XGA Mode: 1024 x 768\r
7d0f2f23	56	#define XGA_H_RES_PIXELS 1024\r
	57	#define XGA_V_RES_PIXELS 768\r
	58	#define XGA_OSC_FREQUENCY 63500000 /* 0x03C8EEE0 */\r
	59	\r
	60	#define XGA_H_SYNC (104 - 1)\r
	61	#define XGA_H_FRONT_PORCH ( 48 - 1)\r
	62	#define XGA_H_BACK_PORCH (152 - 1)\r
	63	\r
	64	#define XGA_V_SYNC ( 4 - 1)\r
	65	#define XGA_V_FRONT_PORCH ( 3 - 1)\r
	66	#define XGA_V_BACK_PORCH ( 23 - 1)\r
	67	\r
7d0f2f23	68	// SXGA Mode: 1280 x 1024\r
7d0f2f23	69	#define SXGA_H_RES_PIXELS 1280\r
	70	#define SXGA_V_RES_PIXELS 1024\r
	71	#define SXGA_OSC_FREQUENCY 109000000 /* 0x067F3540 */\r
	72	\r
	73	#define SXGA_H_SYNC (136 - 1)\r
	74	#define SXGA_H_FRONT_PORCH ( 80 - 1)\r
	75	#define SXGA_H_BACK_PORCH (216 - 1)\r
	76	\r
	77	#define SXGA_V_SYNC ( 7 - 1)\r
	78	#define SXGA_V_FRONT_PORCH ( 3 - 1)\r
	79	#define SXGA_V_BACK_PORCH ( 29 - 1)\r
	80	\r
beeb44f4	81	// WSXGA+ Mode: 1680 x 1050\r
beeb44f4	82	#define WSXGA_H_RES_PIXELS 1680\r
	83	#define WSXGA_V_RES_PIXELS 1050\r
	84	#define WSXGA_OSC_FREQUENCY 147000000 /* 0x08C30AC0 */\r
	85	\r
	86	#define WSXGA_H_SYNC (170 - 1)\r
	87	#define WSXGA_H_FRONT_PORCH (104 - 1)\r
	88	#define WSXGA_H_BACK_PORCH (274 - 1)\r
	89	\r
	90	#define WSXGA_V_SYNC ( 5 - 1)\r
	91	#define WSXGA_V_FRONT_PORCH ( 4 - 1)\r
	92	#define WSXGA_V_BACK_PORCH ( 41 - 1)\r
	93	\r
7d0f2f23	94	// UXGA Mode: 1600 x 1200\r
7d0f2f23	95	#define UXGA_H_RES_PIXELS 1600\r
	96	#define UXGA_V_RES_PIXELS 1200\r
	97	#define UXGA_OSC_FREQUENCY 161000000 /* 0x0998AA40 */\r
	98	\r
	99	#define UXGA_H_SYNC (168 - 1)\r
	100	#define UXGA_H_FRONT_PORCH (112 - 1)\r
	101	#define UXGA_H_BACK_PORCH (280 - 1)\r
	102	\r
	103	#define UXGA_V_SYNC ( 4 - 1)\r
	104	#define UXGA_V_FRONT_PORCH ( 3 - 1)\r
	105	#define UXGA_V_BACK_PORCH ( 38 - 1)\r
	106	\r
7d0f2f23	107	// HD Mode: 1920 x 1080\r
7d0f2f23	108	#define HD_H_RES_PIXELS 1920\r
7d0f2f23	109	#define HD_V_RES_PIXELS 1080\r
deb8a061	110	#define HD_OSC_FREQUENCY 165000000 /* 0x09D5B340 */\r
7d0f2f23	111	\r
deb8a061	112	#define HD_H_SYNC ( 79 - 1)\r
7d0f2f23	113	#define HD_H_FRONT_PORCH (128 - 1)\r
	114	#define HD_H_BACK_PORCH (328 - 1)\r
	115	\r
	116	#define HD_V_SYNC ( 5 - 1)\r
	117	#define HD_V_FRONT_PORCH ( 3 - 1)\r
	118	#define HD_V_BACK_PORCH ( 32 - 1)\r
	119	\r
90347ab3 GP	120	// WVGA Mode: 800 x 480\r
	121	#define WVGA_H_RES_PIXELS 800\r
	122	#define WVGA_V_RES_PIXELS 480\r
	123	#define WVGA_OSC_FREQUENCY 29500000 /* 0x01C22260 */\r
	124	#define WVGA_H_SYNC ( 72 - 1)\r
	125	#define WVGA_H_FRONT_PORCH ( 24 - 1)\r
	126	#define WVGA_H_BACK_PORCH ( 96 - 1)\r
	127	#define WVGA_V_SYNC ( 7 - 1)\r
	128	#define WVGA_V_FRONT_PORCH ( 3 - 1)\r
	129	#define WVGA_V_BACK_PORCH ( 10 - 1)\r
	130	\r
	131	// QHD Mode: 960 x 540\r
	132	#define QHD_H_RES_PIXELS 960\r
	133	#define QHD_V_RES_PIXELS 540\r
	134	#define QHD_OSC_FREQUENCY 40750000 /* 0x026DCBB0 */\r
	135	#define QHD_H_SYNC ( 96 - 1)\r
	136	#define QHD_H_FRONT_PORCH ( 32 - 1)\r
	137	#define QHD_H_BACK_PORCH (128 - 1)\r
	138	#define QHD_V_SYNC ( 5 - 1)\r
	139	#define QHD_V_FRONT_PORCH ( 3 - 1)\r
	140	#define QHD_V_BACK_PORCH ( 14 - 1)\r
	141	\r
	142	// WSVGA Mode: 1024 x 600\r
	143	#define WSVGA_H_RES_PIXELS 1024\r
	144	#define WSVGA_V_RES_PIXELS 600\r
	145	#define WSVGA_OSC_FREQUENCY 49000000 /* 0x02EBAE40 */\r
	146	#define WSVGA_H_SYNC (104 - 1)\r
	147	#define WSVGA_H_FRONT_PORCH ( 40 - 1)\r
	148	#define WSVGA_H_BACK_PORCH (144 - 1)\r
	149	#define WSVGA_V_SYNC ( 10 - 1)\r
	150	#define WSVGA_V_FRONT_PORCH ( 3 - 1)\r
	151	#define WSVGA_V_BACK_PORCH ( 11 - 1)\r
	152	\r
	153	// HD720 Mode: 1280 x 720\r
	154	#define HD720_H_RES_PIXELS 1280\r
	155	#define HD720_V_RES_PIXELS 720\r
	156	#define HD720_OSC_FREQUENCY 74500000 /* 0x0470C7A0 */\r
	157	#define HD720_H_SYNC (128 - 1)\r
	158	#define HD720_H_FRONT_PORCH ( 64 - 1)\r
	159	#define HD720_H_BACK_PORCH (192 - 1)\r
	160	#define HD720_V_SYNC ( 5 - 1)\r
	161	#define HD720_V_FRONT_PORCH ( 3 - 1)\r
	162	#define HD720_V_BACK_PORCH ( 20 - 1)\r
	163	\r
	164	// WXGA Mode: 1280 x 800\r
	165	#define WXGA_H_RES_PIXELS 1280\r
	166	#define WXGA_V_RES_PIXELS 800\r
	167	#define WXGA_OSC_FREQUENCY 83500000 /* 0x04FA1BE0 */\r
	168	#define WXGA_H_SYNC (128 - 1)\r
	169	#define WXGA_H_FRONT_PORCH ( 72 - 1)\r
	170	#define WXGA_H_BACK_PORCH (200 - 1)\r
	171	#define WXGA_V_SYNC ( 6 - 1)\r
	172	#define WXGA_V_FRONT_PORCH ( 3 - 1)\r
	173	#define WXGA_V_BACK_PORCH ( 22 - 1)\r
	174	\r
7d0f2f23	175	// Colour Masks\r
7d0f2f23	176	#define LCD_24BPP_RED_MASK 0x00FF0000\r
	177	#define LCD_24BPP_GREEN_MASK 0x0000FF00\r
	178	#define LCD_24BPP_BLUE_MASK 0x000000FF\r
	179	#define LCD_24BPP_RESERVED_MASK 0xFF000000\r
	180	\r
	181	#define LCD_16BPP_555_RED_MASK 0x00007C00\r
	182	#define LCD_16BPP_555_GREEN_MASK 0x000003E0\r
	183	#define LCD_16BPP_555_BLUE_MASK 0x0000001F\r
	184	#define LCD_16BPP_555_RESERVED_MASK 0x00000000\r
	185	\r
	186	#define LCD_16BPP_565_RED_MASK 0x0000F800\r
	187	#define LCD_16BPP_565_GREEN_MASK 0x000007E0\r
	188	#define LCD_16BPP_565_BLUE_MASK 0x0000001F\r
	189	#define LCD_16BPP_565_RESERVED_MASK 0x00008000\r
	190	\r
	191	#define LCD_12BPP_444_RED_MASK 0x00000F00\r
	192	#define LCD_12BPP_444_GREEN_MASK 0x000000F0\r
	193	#define LCD_12BPP_444_BLUE_MASK 0x0000000F\r
	194	#define LCD_12BPP_444_RESERVED_MASK 0x0000F000\r
	195	\r
4257dfaa	196	/** The enumeration maps the PL111 LcdBpp values used in the LCD Control\r
b1b69d26 GP	197	Register\r
b1b69d26 GP	198	**/\r
7d0f2f23	199	typedef enum {\r
	200	LCD_BITS_PER_PIXEL_1 = 0,\r
	201	LCD_BITS_PER_PIXEL_2,\r
	202	LCD_BITS_PER_PIXEL_4,\r
	203	LCD_BITS_PER_PIXEL_8,\r
	204	LCD_BITS_PER_PIXEL_16_555,\r
	205	LCD_BITS_PER_PIXEL_24,\r
	206	LCD_BITS_PER_PIXEL_16_565,\r
	207	LCD_BITS_PER_PIXEL_12_444\r
	208	} LCD_BPP;\r
	209	\r
262c8846 GP	210	// Display timing settings.\r
	211	typedef struct {\r
	212	UINT32 Resolution;\r
	213	UINT32 Sync;\r
	214	UINT32 BackPorch;\r
	215	UINT32 FrontPorch;\r
	216	} SCAN_TIMINGS;\r
	217	\r
4257dfaa GP	218	/** Platform related initialization function.\r
	219	\r
	220	@param[in] Handle Handle to the LCD device instance.\r
	221	\r
	222	@retval EFI_SUCCESS Plaform library initialized successfully.\r
	223	@retval !(EFI_SUCCESS) Other errors.\r
	224	**/\r
7d0f2f23	225	EFI_STATUS\r
7d0f2f23	226	LcdPlatformInitializeDisplay (\r
6d8d7363	227	IN EFI_HANDLE Handle\r
7d0f2f23	228	);\r
7d0f2f23	229	\r
4257dfaa GP	230	/** Allocate VRAM memory in DRAM for the framebuffer\r
	231	(unless it is reserved already).\r
	232	\r
	233	The allocated address can be used to set the framebuffer.\r
	234	\r
	235	@param[out] VramBaseAddress A pointer to the framebuffer address.\r
	236	@param[out] VramSize A pointer to the size of the frame\r
	237	buffer in bytes\r
	238	\r
	239	@retval EFI_SUCCESS Frame buffer memory allocated successfully.\r
	240	@retval !(EFI_SUCCESS) Other errors.\r
	241	**/\r
7d0f2f23	242	EFI_STATUS\r
	243	LcdPlatformGetVram (\r
	244	OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress,\r
	245	OUT UINTN* VramSize\r
	246	);\r
	247	\r
4257dfaa GP	248	/** Return total number of modes supported.\r
	249	\r
	250	Note: Valid mode numbers are 0 to MaxMode - 1\r
	251	See Section 12.9 of the UEFI Specification 2.7\r
	252	\r
	253	@retval UINT32 Mode Number.\r
	254	**/\r
7d0f2f23	255	UINT32\r
	256	LcdPlatformGetMaxMode (\r
	257	VOID\r
	258	);\r
	259	\r
4257dfaa GP	260	/** Set the requested display mode.\r
	261	\r
	262	@param[in] ModeNumber Mode Number.\r
	263	\r
	264	@retval EFI_SUCCESS Mode set successfully.\r
	265	@retval EFI_INVALID_PARAMETER Requested mode not found.\r
	266	@retval !(EFI_SUCCESS) Other errors.\r
	267	**/\r
7d0f2f23	268	EFI_STATUS\r
	269	LcdPlatformSetMode (\r
	270	IN UINT32 ModeNumber\r
	271	);\r
	272	\r
4257dfaa GP	273	/** Return information for the requested mode number.\r
	274	\r
	275	@param[in] ModeNumber Mode Number.\r
	276	@param[out] Info Pointer for returned mode information\r
	277	(on success).\r
	278	\r
	279	@retval EFI_SUCCESS Mode information for the requested mode\r
	280	returned successfully.\r
	281	@retval EFI_INVALID_PARAMETER Requested mode not found.\r
	282	**/\r
7d0f2f23	283	EFI_STATUS\r
	284	LcdPlatformQueryMode (\r
	285	IN UINT32 ModeNumber,\r
	286	OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info\r
	287	);\r
	288	\r
4257dfaa GP	289	/** Return display timing information for the requested mode number.\r
	290	\r
	291	@param[in] ModeNumber Mode Number.\r
	292	\r
262c8846 GP	293	@param[out] Horizontal Pointer to horizontal timing parameters.\r
	294	(Resolution, Sync, Back porch, Front porch)\r
	295	@param[out] Vertical Pointer to vertical timing parameters.\r
	296	(Resolution, Sync, Back porch, Front porch)\r
	297	\r
4257dfaa GP	298	\r
	299	@retval EFI_SUCCESS Display timing information for the requested\r
	300	mode returned successfully.\r
	301	@retval EFI_INVALID_PARAMETER Requested mode not found.\r
	302	**/\r
7d0f2f23	303	EFI_STATUS\r
	304	LcdPlatformGetTimings (\r
	305	IN UINT32 ModeNumber,\r
262c8846 GP	306	OUT SCAN_TIMINGS **Horizontal,\r
262c8846 GP	307	OUT SCAN_TIMINGS **Vertical\r
7d0f2f23	308	);\r
7d0f2f23	309	\r
4257dfaa GP	310	/** Return bits per pixel information for a mode number.\r
	311	\r
	312	@param[in] ModeNumber Mode Number.\r
	313	\r
	314	@param[out] Bpp Pointer to value bits per pixel information.\r
	315	\r
	316	@retval EFI_SUCCESS Bit per pixel information for the requested\r
	317	mode returned successfully.\r
	318	@retval EFI_INVALID_PARAMETER Requested mode not found.\r
	319	**/\r
7d0f2f23	320	EFI_STATUS\r
	321	LcdPlatformGetBpp (\r
	322	IN UINT32 ModeNumber,\r
	323	OUT LCD_BPP* Bpp\r
	324	);\r
	325	\r
b1b69d26	326	#endif /* LCD_PLATFORM_LIB_H_ */\r