ArmPlatformPkg: Rectify file modes

[mirror_edk2.git] / ArmPlatformPkg / Library / DebugSecExtraActionLib / DebugSecExtraActionLib.c

/** @file\r
*\r
*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
*\r
*  This program and the accompanying materials\r
*  are licensed and made available under the terms and conditions of the BSD License\r
*  which accompanies this distribution.  The full text of the license may be found at\r
*  http://opensource.org/licenses/bsd-license.php\r
*\r
*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
*\r
**/\r
\r
#include <PiPei.h>\r
\r
#include <Library/ArmLib.h>\r
#include <Library/ArmGicLib.h>\r
#include <Library/ArmPlatformLib.h>\r
#include <Library/ArmPlatformSecLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/PrintLib.h>\r
#include <Library/SerialPortLib.h>\r
\r
// When the firmware is built as not Standalone, the secondary cores need to wait the firmware\r
// entirely written into DRAM. It is the firmware from DRAM which will wake up the secondary cores.\r
VOID\r
NonSecureWaitForFirmware (\r
  VOID\r
  )\r
{\r
  VOID (*SecondaryStart)(VOID);\r
  UINTN AcknowledgeInterrupt;\r
  UINTN InterruptId;\r
\r
  // The secondary cores will execute the firmware once wake from WFI.\r
  SecondaryStart = (VOID (*)())(UINTN)PcdGet64 (PcdFvBaseAddress);\r
\r
  ArmCallWFI ();\r
\r
  // Acknowledge the interrupt and send End of Interrupt signal.\r
  AcknowledgeInterrupt = ArmGicAcknowledgeInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), &InterruptId);\r
  // Check if it is a valid interrupt ID\r
  if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGet32 (PcdGicDistributorBase))) {\r
    // Got a valid SGI number hence signal End of Interrupt\r
    ArmGicEndOfInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt);\r
  }\r
\r
  // Jump to secondary core entry point.\r
  SecondaryStart ();\r
\r
  // PEI Core should always load and never return\r
  ASSERT (FALSE);\r
}\r
\r
/**\r
  Call before jumping to Normal World\r
\r
  This function allows the firmware platform to do extra actions before\r
  jumping to the Normal World\r
\r
**/\r
VOID\r
ArmPlatformSecExtraAction (\r
  IN  UINTN         MpId,\r
  OUT UINTN*        JumpAddress\r
  )\r
{\r
  CHAR8           Buffer[100];\r
  UINTN           CharCount;\r
  UINTN*          StartAddress;\r
\r
  if (FeaturePcdGet (PcdStandalone) == FALSE) {\r
\r
    //\r
    // Warning: This code assumes the DRAM has already been initialized by ArmPlatformSecLib\r
    //\r
\r
    if (ArmPlatformIsPrimaryCore (MpId)) {\r
      StartAddress = (UINTN*)(UINTN)PcdGet64 (PcdFvBaseAddress);\r
\r
      // Patch the DRAM to make an infinite loop at the start address\r
      *StartAddress = 0xEAFFFFFE; // opcode for while(1)\r
\r
      CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Waiting for firmware at 0x%08X ...\n\r",StartAddress);\r
      SerialPortWrite ((UINT8 *) Buffer, CharCount);\r
\r
      *JumpAddress = PcdGet64 (PcdFvBaseAddress);\r
    } else {\r
      // When the primary core is stopped by the hardware debugger to copy the firmware\r
      // into DRAM. The secondary cores are still running. As soon as the first bytes of\r
      // the firmware are written into DRAM, the secondary cores will start to execute the\r
      // code even if the firmware is not entirely written into the memory.\r
      // That's why the secondary cores need to be parked in WFI and wake up once the\r
      // firmware is ready.\r
\r
      *JumpAddress = (UINTN)NonSecureWaitForFirmware;\r
    }\r
  } else if (FeaturePcdGet (PcdSystemMemoryInitializeInSec)) {\r
\r
    //\r
    // Warning: This code assumes the DRAM has already been initialized by ArmPlatformSecLib\r
    //\r
\r
    if (ArmPlatformIsPrimaryCore (MpId)) {\r
      // Signal the secondary cores they can jump to PEI phase\r
      ArmGicSendSgiTo (PcdGet32 (PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));\r
\r
      // To enter into Non Secure state, we need to make a return from exception\r
      *JumpAddress = PcdGet64 (PcdFvBaseAddress);\r
    } else {\r
      // We wait for the primary core to finish to initialize the System Memory. Otherwise the secondary\r
      // cores would make crash the system by setting their stacks in DRAM before the primary core has not\r
      // finished to initialize the system memory.\r
      *JumpAddress = (UINTN)NonSecureWaitForFirmware;\r
    }\r
  } else {\r
    *JumpAddress = PcdGet64 (PcdFvBaseAddress);\r
  }\r
}\r