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b1b69d26 | 1 | /** @file\r |
3e7105bb | 2 | \r |
b1b69d26 | 3 | Copyright (c) 2011-2018, ARM Ltd. All rights reserved.<BR>\r |
3e7105bb AB |
4 | \r |
5 | This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #include <Library/DebugLib.h>\r | |
16 | #include <Library/IoLib.h>\r | |
17 | #include <Library/LcdHwLib.h>\r | |
18 | #include <Library/LcdPlatformLib.h>\r | |
19 | #include <Library/MemoryAllocationLib.h>\r | |
20 | #include <Library/PcdLib.h>\r | |
21 | \r | |
22 | #include "HdLcd.h"\r | |
23 | \r | |
b1b69d26 GP |
24 | /** This file contains all the bits of the Lcd that are\r |
25 | platform independent.\r | |
26 | **/\r | |
3e7105bb AB |
27 | \r |
28 | STATIC\r | |
29 | UINTN\r | |
30 | GetBytesPerPixel (\r | |
31 | IN LCD_BPP Bpp\r | |
32 | )\r | |
33 | {\r | |
b1b69d26 | 34 | switch (Bpp) {\r |
3e7105bb AB |
35 | case LCD_BITS_PER_PIXEL_24:\r |
36 | return 4;\r | |
37 | \r | |
38 | case LCD_BITS_PER_PIXEL_16_565:\r | |
39 | case LCD_BITS_PER_PIXEL_16_555:\r | |
40 | case LCD_BITS_PER_PIXEL_12_444:\r | |
41 | return 2;\r | |
42 | \r | |
43 | case LCD_BITS_PER_PIXEL_8:\r | |
44 | case LCD_BITS_PER_PIXEL_4:\r | |
45 | case LCD_BITS_PER_PIXEL_2:\r | |
46 | case LCD_BITS_PER_PIXEL_1:\r | |
47 | return 1;\r | |
48 | \r | |
49 | default:\r | |
50 | return 0;\r | |
51 | }\r | |
52 | }\r | |
53 | \r | |
54 | EFI_STATUS\r | |
55 | LcdInitialize (\r | |
56 | IN EFI_PHYSICAL_ADDRESS VramBaseAddress\r | |
57 | )\r | |
58 | {\r | |
59 | // Disable the controller\r | |
b1b69d26 | 60 | MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_DISABLE);\r |
3e7105bb AB |
61 | \r |
62 | // Disable all interrupts\r | |
b1b69d26 | 63 | MmioWrite32 (HDLCD_REG_INT_MASK, 0);\r |
3e7105bb AB |
64 | \r |
65 | // Define start of the VRAM. This never changes for any graphics mode\r | |
b1b69d26 | 66 | MmioWrite32 (HDLCD_REG_FB_BASE, (UINT32)VramBaseAddress);\r |
3e7105bb AB |
67 | \r |
68 | // Setup various registers that never change\r | |
b1b69d26 GP |
69 | MmioWrite32 (HDLCD_REG_BUS_OPTIONS, (4 << 8) | HDLCD_BURST_8);\r |
70 | \r | |
71 | MmioWrite32 (HDLCD_REG_POLARITIES, HDLCD_DEFAULT_POLARITIES);\r | |
72 | \r | |
73 | MmioWrite32 (\r | |
74 | HDLCD_REG_PIXEL_FORMAT,\r | |
75 | HDLCD_LITTLE_ENDIAN | HDLCD_4BYTES_PER_PIXEL\r | |
76 | );\r | |
77 | \r | |
78 | MmioWrite32 (HDLCD_REG_RED_SELECT, (0 << 16 | 8 << 8 | 0));\r | |
79 | MmioWrite32 (HDLCD_REG_GREEN_SELECT, (0 << 16 | 8 << 8 | 8));\r | |
80 | MmioWrite32 (HDLCD_REG_BLUE_SELECT, (0 << 16 | 8 << 8 | 16));\r | |
3e7105bb AB |
81 | \r |
82 | return EFI_SUCCESS;\r | |
83 | }\r | |
84 | \r | |
85 | EFI_STATUS\r | |
86 | LcdSetMode (\r | |
87 | IN UINT32 ModeNumber\r | |
88 | )\r | |
89 | {\r | |
90 | EFI_STATUS Status;\r | |
91 | UINT32 HRes;\r | |
92 | UINT32 HSync;\r | |
93 | UINT32 HBackPorch;\r | |
94 | UINT32 HFrontPorch;\r | |
95 | UINT32 VRes;\r | |
96 | UINT32 VSync;\r | |
97 | UINT32 VBackPorch;\r | |
98 | UINT32 VFrontPorch;\r | |
99 | UINT32 BytesPerPixel;\r | |
100 | LCD_BPP LcdBpp;\r | |
101 | \r | |
3e7105bb | 102 | // Set the video mode timings and other relevant information\r |
b1b69d26 GP |
103 | Status = LcdPlatformGetTimings (\r |
104 | ModeNumber,\r | |
105 | &HRes,\r | |
106 | &HSync,\r | |
107 | &HBackPorch,\r | |
108 | &HFrontPorch,\r | |
109 | &VRes,\r | |
110 | &VSync,\r | |
111 | &VBackPorch,\r | |
112 | &VFrontPorch\r | |
113 | );\r | |
3e7105bb | 114 | ASSERT_EFI_ERROR (Status);\r |
b1b69d26 | 115 | if (EFI_ERROR (Status)) {\r |
3e7105bb AB |
116 | return EFI_DEVICE_ERROR;\r |
117 | }\r | |
118 | \r | |
b1b69d26 | 119 | Status = LcdPlatformGetBpp (ModeNumber, &LcdBpp);\r |
3e7105bb | 120 | ASSERT_EFI_ERROR (Status);\r |
b1b69d26 | 121 | if (EFI_ERROR (Status)) {\r |
3e7105bb AB |
122 | return EFI_DEVICE_ERROR;\r |
123 | }\r | |
124 | \r | |
b1b69d26 | 125 | BytesPerPixel = GetBytesPerPixel (LcdBpp);\r |
3e7105bb AB |
126 | \r |
127 | // Disable the controller\r | |
b1b69d26 | 128 | MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_DISABLE);\r |
3e7105bb AB |
129 | \r |
130 | // Update the frame buffer information with the new settings\r | |
b1b69d26 GP |
131 | MmioWrite32 (HDLCD_REG_FB_LINE_LENGTH, HRes * BytesPerPixel);\r |
132 | MmioWrite32 (HDLCD_REG_FB_LINE_PITCH, HRes * BytesPerPixel);\r | |
133 | MmioWrite32 (HDLCD_REG_FB_LINE_COUNT, VRes - 1);\r | |
3e7105bb AB |
134 | \r |
135 | // Set the vertical timing information\r | |
b1b69d26 GP |
136 | MmioWrite32 (HDLCD_REG_V_SYNC, VSync);\r |
137 | MmioWrite32 (HDLCD_REG_V_BACK_PORCH, VBackPorch);\r | |
138 | MmioWrite32 (HDLCD_REG_V_DATA, VRes - 1);\r | |
139 | MmioWrite32 (HDLCD_REG_V_FRONT_PORCH, VFrontPorch);\r | |
3e7105bb AB |
140 | \r |
141 | // Set the horizontal timing information\r | |
b1b69d26 GP |
142 | MmioWrite32 (HDLCD_REG_H_SYNC, HSync);\r |
143 | MmioWrite32 (HDLCD_REG_H_BACK_PORCH, HBackPorch);\r | |
144 | MmioWrite32 (HDLCD_REG_H_DATA, HRes - 1);\r | |
145 | MmioWrite32 (HDLCD_REG_H_FRONT_PORCH, HFrontPorch);\r | |
3e7105bb AB |
146 | \r |
147 | // Enable the controller\r | |
b1b69d26 | 148 | MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_ENABLE);\r |
3e7105bb AB |
149 | \r |
150 | return EFI_SUCCESS;\r | |
151 | }\r | |
152 | \r | |
153 | VOID\r | |
154 | LcdShutdown (\r | |
155 | VOID\r | |
156 | )\r | |
157 | {\r | |
158 | // Disable the controller\r | |
159 | MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_DISABLE);\r | |
160 | }\r | |
161 | \r | |
162 | EFI_STATUS\r | |
163 | LcdIdentify (\r | |
164 | VOID\r | |
165 | )\r | |
166 | {\r | |
167 | return EFI_SUCCESS;\r | |
168 | }\r |