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1d5d0ae9 1//\r
bebda7ce 2// Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
1d5d0ae9 3//\r
3402aac7
RC
4// This program and the accompanying materials\r
5// are licensed and made available under the terms and conditions of the BSD License\r
6// which accompanies this distribution. The full text of the license may be found at\r
7// http://opensource.org/licenses/bsd-license.php\r
8//\r
9// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
10// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
1d5d0ae9 11//\r
12//\r
13\r
14#include <AsmMacroIoLib.h>\r
15#include <Base.h>\r
16#include <Library/PcdLib.h>\r
17#include <AutoGen.h>\r
18\r
19 INCLUDE AsmMacroIoLib.inc\r
3402aac7 20\r
1d5d0ae9 21 IMPORT CEntryPoint\r
2d45f194 22 IMPORT ArmPlatformGetCorePosition\r
bebda7ce 23 IMPORT ArmPlatformIsPrimaryCore\r
0787bc61 24 IMPORT ArmReadMpidr\r
b5a57223 25 IMPORT ArmPlatformPeiBootAction\r
1d5d0ae9 26 EXPORT _ModuleEntryPoint\r
3402aac7 27\r
1d5d0ae9 28 PRESERVE8\r
29 AREA PrePeiCoreEntryPoint, CODE, READONLY\r
3402aac7 30\r
1d5d0ae9 31StartupAddr DCD CEntryPoint\r
32\r
1d5d0ae9 33_ModuleEntryPoint\r
b5a57223 34 // Do early platform specific actions\r
35 bl ArmPlatformPeiBootAction\r
36\r
1d5d0ae9 37 // Identify CPU ID\r
0787bc61 38 bl ArmReadMpidr\r
bebda7ce 39 // Keep a copy of the MpId register value\r
40 mov r5, r0\r
3402aac7 41\r
bebda7ce 42 // Is it the Primary Core ?\r
91c38d4e 43 bl ArmPlatformIsPrimaryCore\r
bebda7ce 44\r
1377db63 45 // Get the top of the primary stacks (and the base of the secondary stacks)\r
2dbcb8f0 46 LoadConstantToReg (FixedPcdGet32(PcdCPUCoresStackBase), r1)\r
47 LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)\r
1377db63 48 add r1, r1, r2\r
2dbcb8f0 49\r
bebda7ce 50 // r0 is equal to 1 if I am the primary core\r
51 cmp r0, #1\r
2dbcb8f0 52 beq _SetupPrimaryCoreStack\r
53\r
54_SetupSecondaryCoreStack\r
1377db63 55 // r1 contains the base of the secondary stacks\r
2dbcb8f0 56\r
2d45f194 57 // Get the Core Position\r
58 mov r6, r1 // Save base of the secondary stacks\r
59 mov r0, r5\r
60 bl ArmPlatformGetCorePosition\r
2dbcb8f0 61 // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r
1377db63 62 add r0, r0, #1\r
1d5d0ae9 63\r
2dbcb8f0 64 // StackOffset = CorePos * StackSize\r
1377db63 65 LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r2)\r
66 mul r0, r0, r2\r
2dbcb8f0 67 // SP = StackBase + StackOffset\r
2d45f194 68 add sp, r6, r0\r
47a8e12f 69\r
70_PrepareArguments\r
1d5d0ae9 71 // The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector\r
f92b93c9 72 LoadConstantToReg (FixedPcdGet32(PcdFvBaseAddress), r2)\r
1d5d0ae9 73 add r2, r2, #4\r
74 ldr r1, [r2]\r
75\r
1377db63 76 // Move sec startup address into a data register\r
77 // Ensure we're jumping to FV version of the code (not boot remapped alias)\r
78 ldr r3, StartupAddr\r
3402aac7 79\r
1377db63 80 // Jump to PrePeiCore C code\r
0787bc61 81 // r0 = mp_id\r
1d5d0ae9 82 // r1 = pei_core_address\r
1377db63 83 mov r0, r5\r
84 blx r3\r
85\r
86_SetupPrimaryCoreStack\r
87 // r1 contains the top of the primary stack\r
88 LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), r2)\r
89\r
90 // The reserved space for global variable must be 8-bytes aligned for pushing\r
91 // 64-bit variable on the stack\r
92 SetPrimaryStack (r1, r2, r3)\r
93 b _PrepareArguments\r
1d5d0ae9 94\r
2dbcb8f0 95_NeverReturn\r
96 b _NeverReturn\r
97\r
1d5d0ae9 98 END\r