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ArmPlatformPkg/ArmPlatformLib: Added support for ArmPlatformIsPrimaryCore()
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cd872e40 1//\r
063ad84e 2// Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
cd872e40 3//\r
4// This program and the accompanying materials\r
5// are licensed and made available under the terms and conditions of the BSD License\r
6// which accompanies this distribution. The full text of the license may be found at\r
7// http://opensource.org/licenses/bsd-license.php\r
8//\r
9// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
10// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
11//\r
12//\r
13\r
14#include <AsmMacroIoLib.h>\r
15#include <Base.h>\r
16#include <Library/PcdLib.h>\r
17#include <AutoGen.h>\r
18\r
063ad84e 19#include <Chipset/ArmV7.h>\r
20\r
cd872e40 21 INCLUDE AsmMacroIoLib.inc\r
22 \r
23 IMPORT CEntryPoint\r
bebda7ce 24 IMPORT ArmPlatformIsPrimaryCore\r
0787bc61 25 IMPORT ArmReadMpidr\r
695df8ba 26 IMPORT ArmPlatformStackSet\r
27 \r
cd872e40 28 EXPORT _ModuleEntryPoint\r
29\r
30 PRESERVE8\r
31 AREA PrePiCoreEntryPoint, CODE, READONLY\r
32 \r
33StartupAddr DCD CEntryPoint\r
34\r
35_ModuleEntryPoint\r
0787bc61 36 // Get ID of this CPU in Multicore system\r
37 bl ArmReadMpidr\r
bebda7ce 38 // Keep a copy of the MpId register value\r
39 mov r6, r0\r
cd872e40 40\r
d269095b 41_SetSVCMode\r
99565b88 42 // Enter SVC mode, Disable FIQ and IRQ\r
063ad84e 43 mov r1, #(CPSR_MODE_SVC :OR: CPSR_IRQ :OR: CPSR_FIQ)\r
d269095b 44 msr CPSR_c, r1\r
45\r
2dbcb8f0 46// Check if we can install the stack at the top of the System Memory or if we need\r
d269095b 47// to install the stacks at the bottom of the Firmware Device (case the FD is located\r
48// at the top of the DRAM)\r
49_SetupStackPosition\r
cd872e40 50 // Compute Top of System Memory\r
51 LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryBase), r1)\r
52 LoadConstantToReg (FixedPcdGet32(PcdSystemMemorySize), r2)\r
2569b068 53 sub r2, r2, #1\r
cd872e40 54 add r1, r1, r2 // r1 = SystemMemoryTop = PcdSystemMemoryBase + PcdSystemMemorySize\r
cd872e40 55\r
d269095b 56 // Calculate Top of the Firmware Device\r
f92b93c9 57 LoadConstantToReg (FixedPcdGet32(PcdFdBaseAddress), r2)\r
58 LoadConstantToReg (FixedPcdGet32(PcdFdSize), r3)\r
2569b068 59 sub r3, r3, #1\r
7defe7b3 60 add r3, r3, r2 // r3 = FdTop = PcdFdBaseAddress + PcdFdSize\r
d269095b 61\r
62 // UEFI Memory Size (stacks are allocated in this region)\r
63 LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryUefiRegionSize), r4)\r
64\r
65 //\r
66 // Reserve the memory for the UEFI region (contain stacks on its top)\r
67 //\r
68\r
69 // Calculate how much space there is between the top of the Firmware and the Top of the System Memory\r
2dbcb8f0 70 subs r0, r1, r3 // r0 = SystemMemoryTop - FdTop\r
71 bmi _SetupStack // Jump if negative (FdTop > SystemMemoryTop). Case when the PrePi is in XIP memory outside of the DRAM\r
72 cmp r0, r4\r
d269095b 73 bge _SetupStack\r
74\r
75 // Case the top of stacks is the FdBaseAddress\r
76 mov r1, r2\r
cd872e40 77\r
78_SetupStack\r
2dbcb8f0 79 // r1 contains the top of the stack (and the UEFI Memory)\r
d269095b 80\r
2569b068 81 // Because the 'push' instruction is equivalent to 'stmdb' (decrement before), we need to increment\r
82 // one to the top of the stack. We check if incrementing one does not overflow (case of DRAM at the\r
83 // top of the memory space)\r
17839a45 84 adds r7, r1, #1\r
2569b068 85 bcs _SetupOverflowStack\r
86\r
87_SetupAlignedStack\r
17839a45 88 mov r1, r7\r
2569b068 89 b _GetBaseUefiMemory\r
90\r
91_SetupOverflowStack\r
92 // Case memory at the top of the address space. Ensure the top of the stack is EFI_PAGE_SIZE\r
93 // aligned (4KB)\r
17839a45 94 LoadConstantToReg (EFI_PAGE_MASK, r7)\r
95 and r7, r7, r1\r
96 sub r1, r1, r7\r
2569b068 97\r
98_GetBaseUefiMemory\r
d269095b 99 // Calculate the Base of the UEFI Memory\r
17839a45 100 sub r7, r1, r4\r
cd872e40 101\r
2dbcb8f0 102_GetStackBase\r
1377db63 103 // r1 = The top of the Mpcore Stacks\r
2dbcb8f0 104 // Stack for the primary core = PrimaryCoreStack\r
105 LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)\r
695df8ba 106 sub r8, r1, r2\r
107\r
108 // Stack for the secondary core = Number of Cores - 1\r
109 LoadConstantToReg (FixedPcdGet32(PcdCoreCount), r0)\r
110 sub r0, r0, #1\r
111 LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r1)\r
112 mul r1, r1, r0\r
113 sub r8, r8, r1\r
114\r
115 // r8 = The base of the MpCore Stacks (primary stack & secondary stacks)\r
116 mov r0, r8\r
117 mov r1, r6\r
118 //ArmPlatformStackSet(StackBase, MpId, PrimaryStackSize, SecondaryStackSize)\r
119 LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)\r
2dbcb8f0 120 LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r3)\r
17839a45 121 bl ArmPlatformStackSet\r
2dbcb8f0 122\r
123 // Is it the Primary Core ?\r
bebda7ce 124 mov r0, r6\r
125 bl ArmPlatformIsPrimaryCore\r
126 cmp r0, #1\r
cd872e40 127 bne _PrepareArguments\r
128\r
17839a45 129_ReserveGlobalVariable\r
130 LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), r0)\r
131 // InitializePrimaryStack($GlobalVariableSize, $Tmp1)\r
132 InitializePrimaryStack r0, r1\r
2dbcb8f0 133\r
cd872e40 134_PrepareArguments\r
17839a45 135 mov r0, r6\r
136 mov r1, r7\r
137 mov r2, r8\r
c524ffbb 138 mov r3, sp\r
139\r
cd872e40 140 // Move sec startup address into a data register\r
141 // Ensure we're jumping to FV version of the code (not boot remapped alias)\r
c524ffbb 142 ldr r4, StartupAddr\r
cd872e40 143\r
d269095b 144 // Jump to PrePiCore C code\r
0787bc61 145 // r0 = MpId\r
cd872e40 146 // r1 = UefiMemoryBase\r
c524ffbb 147 // r2 = StacksBase\r
148 // r3 = GlobalVariableBase\r
149 blx r4\r
cd872e40 150\r
2dbcb8f0 151_NeverReturn\r
152 b _NeverReturn\r
153\r
cd872e40 154 END\r