ArmPlatformPkg: Change the memory model for the ARM Platform components

[mirror_edk2.git] / ArmPlatformPkg / PrePi / MainMPCore.c

/** @file\r
*\r
*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
*\r
*  This program and the accompanying materials\r
*  are licensed and made available under the terms and conditions of the BSD License\r
*  which accompanies this distribution.  The full text of the license may be found at\r
*  http://opensource.org/licenses/bsd-license.php\r
*\r
*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
*\r
**/\r
\r
#include "PrePi.h"\r
\r
#include <Library/ArmMPCoreMailBoxLib.h>\r
#include <Chipset/ArmV7.h>\r
#include <Drivers/PL390Gic.h>\r
\r
VOID\r
PrimaryMain (\r
  IN  UINTN                     UefiMemoryBase,\r
  IN  UINT64                    StartTimeStamp\r
  )\r
{\r
  //Enable the GIC Distributor\r
  PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase));\r
\r
  // In some cases, the secondary cores are waiting for an SGI from the next stage boot loader toresume their initialization\r
  if (!FixedPcdGet32(PcdSendSgiToBringUpSecondaryCores)) {\r
    // Sending SGI to all the Secondary CPU interfaces\r
    PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
  }\r
\r
  PrePiMain (UefiMemoryBase, StartTimeStamp);\r
\r
  // We must never return\r
  ASSERT(FALSE);\r
}\r
\r
VOID\r
SecondaryMain (\r
  IN  UINTN                     CoreId\r
  )\r
{\r
  // Function pointer to Secondary Core entry point\r
  VOID (*secondary_start)(VOID);\r
  UINTN secondary_entry_addr=0;\r
\r
  // Clear Secondary cores MailBox\r
  ArmClearMPCoreMailbox();\r
\r
  while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {\r
    ArmCallWFI();\r
    // Acknowledge the interrupt and send End of Interrupt signal.\r
    PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);\r
  }\r
\r
  secondary_start = (VOID (*)())secondary_entry_addr;\r
\r
  // Jump to secondary core entry point.\r
  secondary_start();\r
\r
  // The secondaries shouldn't reach here\r
  ASSERT(FALSE);\r
}\r