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1d5d0ae9 | 1 | /** @file |
009f583f | 2 | * Main file supporting the SEC Phase on ARM Platforms |
1d5d0ae9 | 3 | * |
4 | * Copyright (c) 2011, ARM Limited. All rights reserved. | |
5 | * | |
6 | * This program and the accompanying materials | |
7 | * are licensed and made available under the terms and conditions of the BSD License | |
8 | * which accompanies this distribution. The full text of the license may be found at | |
9 | * http://opensource.org/licenses/bsd-license.php | |
10 | * | |
11 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
12 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
13 | * | |
14 | **/ | |
15 | ||
a6caee65 | 16 | #include <Library/DebugAgentLib.h> |
2637d1ef | 17 | #include <Library/PrintLib.h> |
1d5d0ae9 | 18 | #include <Library/BaseMemoryLib.h> |
1d5d0ae9 | 19 | #include <Library/SerialPortLib.h> |
20 | #include <Library/ArmPlatformLib.h> | |
55a0d64b | 21 | #include <Library/ArmGicLib.h> |
90d6a1bb | 22 | #include <Library/ArmCpuLib.h> |
0620eec9 | 23 | |
009f583f | 24 | #include "SecInternal.h" |
25 | ||
e862cd50 | 26 | #define SerialPrint(txt) SerialPortWrite ((UINT8*)txt, AsciiStrLen(txt)+1); |
2637d1ef | 27 | |
1d5d0ae9 | 28 | extern VOID *monitor_vector_table; |
29 | ||
1d5d0ae9 | 30 | VOID |
31 | CEntryPoint ( | |
0787bc61 | 32 | IN UINTN MpId |
1d5d0ae9 | 33 | ) |
34 | { | |
2637d1ef | 35 | CHAR8 Buffer[100]; |
36 | UINTN CharCount; | |
a6caee65 | 37 | UINTN JumpAddress; |
2637d1ef | 38 | |
1d5d0ae9 | 39 | // Primary CPU clears out the SCU tag RAMs, secondaries wait |
0787bc61 | 40 | if (IS_PRIMARY_CORE(MpId)) { |
90d6a1bb | 41 | ArmCpuSetup (MpId); |
42 | ||
43 | if (ArmIsMpCore()) { | |
44 | ArmCpuSynchronizeSignal (ARM_CPU_EVENT_BOOT_MEM_INIT); | |
1d5d0ae9 | 45 | } |
46 | ||
47 | // SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib | |
48 | // In non SEC modules the init call is in autogenerated code. | |
49 | SerialPortInitialize (); | |
2637d1ef | 50 | |
1d5d0ae9 | 51 | // Start talking |
2637d1ef | 52 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"UEFI firmware built at %a on %a\n\r",__TIME__, __DATE__); |
53 | SerialPortWrite ((UINT8 *) Buffer, CharCount); | |
1d5d0ae9 | 54 | |
a6caee65 | 55 | // Initialize the Debug Agent for Source Level Debugging |
56 | InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL); | |
57 | SaveAndSetDebugTimerInterrupt (TRUE); | |
58 | ||
1d5d0ae9 | 59 | // Now we've got UART, make the check: |
60 | // - The Vector table must be 32-byte aligned | |
61 | ASSERT(((UINT32)SecVectorTable & ((1 << 5)-1)) == 0); | |
90d6a1bb | 62 | |
63 | // Enable the GIC distributor and CPU Interface | |
64 | // - no other Interrupts are enabled, doesn't have to worry about the priority. | |
65 | // - all the cores are in secure state, use secure SGI's | |
66 | ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase)); | |
67 | ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase)); | |
68 | } else { | |
69 | // Enable the GIC CPU Interface | |
70 | ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase)); | |
1d5d0ae9 | 71 | } |
72 | ||
73 | // Invalidate the data cache. Doesn't have to do the Data cache clean. | |
74 | ArmInvalidateDataCache(); | |
75 | ||
009f583f | 76 | // Invalidate Instruction Cache |
1d5d0ae9 | 77 | ArmInvalidateInstructionCache(); |
78 | ||
009f583f | 79 | // Invalidate I & D TLBs |
1d5d0ae9 | 80 | ArmInvalidateInstructionAndDataTlb(); |
81 | ||
82 | // Enable Full Access to CoProcessors | |
83 | ArmWriteCPACR (CPACR_CP_FULL_ACCESS); | |
84 | ||
90d6a1bb | 85 | if (FixedPcdGet32 (PcdVFPEnabled)) { |
1d5d0ae9 | 86 | ArmEnableVFP(); |
87 | } | |
88 | ||
0787bc61 | 89 | if (IS_PRIMARY_CORE(MpId)) { |
8e06b586 | 90 | // Initialize peripherals that must be done at the early stage |
91 | // Example: Some L2x0 controllers must be initialized in Secure World | |
aa01abaa | 92 | ArmPlatformSecInitialize (); |
1d5d0ae9 | 93 | |
94 | // If we skip the PEI Core we could want to initialize the DRAM in the SEC phase. | |
95 | // If we are in standalone, we need the initialization to copy the UEFI firmware into DRAM | |
90d6a1bb | 96 | if (FeaturePcdGet (PcdSystemMemoryInitializeInSec)) { |
1d5d0ae9 | 97 | // Initialize system memory (DRAM) |
1ad14bc8 | 98 | ArmPlatformInitializeSystemMemory (); |
1d5d0ae9 | 99 | } |
100 | ||
0620eec9 | 101 | // Some platform can change their physical memory mapping |
1ad14bc8 | 102 | ArmPlatformBootRemapping (); |
1d5d0ae9 | 103 | } |
104 | ||
105 | // Test if Trustzone is supported on this platform | |
009f583f | 106 | if (ArmPlatformTrustzoneSupported ()) { |
107 | // Ensure the Monitor Stack Base & Size have been set | |
108 | ASSERT(PcdGet32(PcdCPUCoresSecMonStackBase) != 0); | |
109 | ASSERT(PcdGet32(PcdCPUCoreSecMonStackSize) != 0); | |
110 | ||
90d6a1bb | 111 | if (ArmIsMpCore()) { |
1d5d0ae9 | 112 | // Setup SMP in Non Secure world |
90d6a1bb | 113 | ArmCpuSetupSmpNonSecure (GET_CORE_ID(MpId)); |
1d5d0ae9 | 114 | } |
115 | ||
116 | // Enter Monitor Mode | |
0787bc61 | 117 | enter_monitor_mode ((VOID*)(PcdGet32(PcdCPUCoresSecMonStackBase) + (PcdGet32(PcdCPUCoreSecMonStackSize) * GET_CORE_POS(MpId)))); |
1d5d0ae9 | 118 | |
119 | //Write the monitor mode vector table address | |
120 | ArmWriteVMBar((UINT32) &monitor_vector_table); | |
121 | ||
122 | //-------------------- Monitor Mode --------------------- | |
0620eec9 | 123 | // Setup the Trustzone Chipsets |
0787bc61 | 124 | if (IS_PRIMARY_CORE(MpId)) { |
009f583f | 125 | ArmPlatformTrustzoneInit (); |
1d5d0ae9 | 126 | |
90d6a1bb | 127 | // Waiting for the Primary Core to have finished to initialize the Secure World |
128 | ArmCpuSynchronizeSignal (ARM_CPU_EVENT_SECURE_INIT); | |
1d5d0ae9 | 129 | } else { |
130 | // The secondary cores need to wait until the Trustzone chipsets configuration is done | |
0620eec9 | 131 | // before switching to Non Secure World |
1d5d0ae9 | 132 | |
90d6a1bb | 133 | // Waiting for the Primary Core to have finished to initialize the Secure World |
134 | ArmCpuSynchronizeWait (ARM_CPU_EVENT_SECURE_INIT); | |
1d5d0ae9 | 135 | } |
136 | ||
137 | // Transfer the interrupt to Non-secure World | |
90d6a1bb | 138 | ArmGicSetupNonSecure (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase)); |
1d5d0ae9 | 139 | |
140 | // Write to CP15 Non-secure Access Control Register : | |
141 | // - Enable CP10 and CP11 accesses in NS World | |
142 | // - Enable Access to Preload Engine in NS World | |
143 | // - Enable lockable TLB entries allocation in NS world | |
144 | // - Enable R/W access to SMP bit of Auxiliary Control Register in NS world | |
009f583f | 145 | ArmWriteNsacr (NSACR_NS_SMP | NSACR_TL | NSACR_PLE | NSACR_CP(10) | NSACR_CP(11)); |
1d5d0ae9 | 146 | |
147 | // CP15 Secure Configuration Register with Non Secure bit (SCR_NS), CPSR.A modified in any | |
148 | // security state (SCR_AW), CPSR.F modified in any security state (SCR_FW) | |
009f583f | 149 | ArmWriteScr (SCR_NS | SCR_FW | SCR_AW); |
1d5d0ae9 | 150 | } else { |
0787bc61 | 151 | if (IS_PRIMARY_CORE(MpId)) { |
2637d1ef | 152 | SerialPrint ("Trust Zone Configuration is disabled\n\r"); |
1d5d0ae9 | 153 | } |
154 | ||
1d5d0ae9 | 155 | // With Trustzone support the transition from Sec to Normal world is done by return_from_exception(). |
156 | // If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program | |
157 | // Status Register as the the current one (CPSR). | |
a6caee65 | 158 | copy_cpsr_into_spsr (); |
1d5d0ae9 | 159 | } |
160 | ||
f92b93c9 | 161 | JumpAddress = PcdGet32 (PcdFvBaseAddress); |
0787bc61 | 162 | ArmPlatformSecExtraAction (MpId, &JumpAddress); |
64e03133 | 163 | |
a6caee65 | 164 | return_from_exception (JumpAddress); |
1d5d0ae9 | 165 | //-------------------- Non Secure Mode --------------------- |
166 | ||
167 | // PEI Core should always load and never return | |
168 | ASSERT (FALSE); | |
169 | } | |
170 | ||
2637d1ef | 171 | VOID |
172 | SecCommonExceptionEntry ( | |
173 | IN UINT32 Entry, | |
174 | IN UINT32 LR | |
175 | ) | |
176 | { | |
177 | CHAR8 Buffer[100]; | |
178 | UINTN CharCount; | |
179 | ||
1d5d0ae9 | 180 | switch (Entry) { |
181 | case 0: | |
2637d1ef | 182 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reset Exception at 0x%X\n\r",LR); |
1d5d0ae9 | 183 | break; |
184 | case 1: | |
2637d1ef | 185 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Undefined Exception at 0x%X\n\r",LR); |
1d5d0ae9 | 186 | break; |
187 | case 2: | |
2637d1ef | 188 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"SWI Exception at 0x%X\n\r",LR); |
1d5d0ae9 | 189 | break; |
190 | case 3: | |
2637d1ef | 191 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"PrefetchAbort Exception at 0x%X\n\r",LR); |
1d5d0ae9 | 192 | break; |
193 | case 4: | |
2637d1ef | 194 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"DataAbort Exception at 0x%X\n\r",LR); |
1d5d0ae9 | 195 | break; |
196 | case 5: | |
2637d1ef | 197 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reserved Exception at 0x%X\n\r",LR); |
1d5d0ae9 | 198 | break; |
199 | case 6: | |
2637d1ef | 200 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"IRQ Exception at 0x%X\n\r",LR); |
1d5d0ae9 | 201 | break; |
202 | case 7: | |
2637d1ef | 203 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"FIQ Exception at 0x%X\n\r",LR); |
1d5d0ae9 | 204 | break; |
205 | default: | |
2637d1ef | 206 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Unknown Exception at 0x%X\n\r",LR); |
1d5d0ae9 | 207 | break; |
208 | } | |
2637d1ef | 209 | SerialPortWrite ((UINT8 *) Buffer, CharCount); |
1d5d0ae9 | 210 | while(1); |
211 | } |