ArmPkg: Renamed library 'PL390GicLib' into 'ArmGicLib'
[mirror_edk2.git] / ArmPlatformPkg / Sec / Sec.c
CommitLineData
1d5d0ae9 1/** @file
2* Main file supporting the SEC Phase for Versatile Express
3*
4* Copyright (c) 2011, ARM Limited. All rights reserved.
5*
6* This program and the accompanying materials
7* are licensed and made available under the terms and conditions of the BSD License
8* which accompanies this distribution. The full text of the license may be found at
9* http://opensource.org/licenses/bsd-license.php
10*
11* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13*
14**/
15
16#include <Library/DebugLib.h>
a6caee65 17#include <Library/DebugAgentLib.h>
1d5d0ae9 18#include <Library/PcdLib.h>
2637d1ef 19#include <Library/PrintLib.h>
1d5d0ae9 20#include <Library/BaseLib.h>
21#include <Library/BaseMemoryLib.h>
22#include <Library/ArmLib.h>
1d5d0ae9 23#include <Library/SerialPortLib.h>
24#include <Library/ArmPlatformLib.h>
25
0620eec9 26#include <Chipset/ArmV7.h>
55a0d64b 27#include <Library/ArmGicLib.h>
0620eec9 28
29#define ARM_PRIMARY_CORE 0
30
e862cd50 31#define SerialPrint(txt) SerialPortWrite ((UINT8*)txt, AsciiStrLen(txt)+1);
2637d1ef 32
1d5d0ae9 33extern VOID *monitor_vector_table;
34
0620eec9 35VOID
36ArmSetupGicNonSecure (
37 IN INTN GicDistributorBase,
38 IN INTN GicInterruptInterfaceBase
1d5d0ae9 39);
40
41// Vector Table for Sec Phase
0620eec9 42VOID
43SecVectorTable (
44 VOID
45 );
1d5d0ae9 46
0620eec9 47VOID
48NonSecureWaitForFirmware (
1d5d0ae9 49 VOID
50 );
51
52VOID
53enter_monitor_mode(
54 IN VOID* Stack
55 );
56
57VOID
58return_from_exception (
59 IN UINTN NonSecureBase
60 );
61
62VOID
63copy_cpsr_into_spsr (
64 VOID
65 );
66
67VOID
68CEntryPoint (
69 IN UINTN CoreId
70 )
71{
2637d1ef 72 CHAR8 Buffer[100];
73 UINTN CharCount;
a6caee65 74 UINTN JumpAddress;
2637d1ef 75
1d5d0ae9 76 // Primary CPU clears out the SCU tag RAMs, secondaries wait
0620eec9 77 if (CoreId == ARM_PRIMARY_CORE) {
1d5d0ae9 78 if (FixedPcdGet32(PcdMPCoreSupport)) {
79 ArmInvalidScu();
80 }
81
82 // SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib
83 // In non SEC modules the init call is in autogenerated code.
84 SerialPortInitialize ();
2637d1ef 85
1d5d0ae9 86 // Start talking
2637d1ef 87 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"UEFI firmware built at %a on %a\n\r",__TIME__, __DATE__);
88 SerialPortWrite ((UINT8 *) Buffer, CharCount);
1d5d0ae9 89
a6caee65 90 // Initialize the Debug Agent for Source Level Debugging
91 InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL);
92 SaveAndSetDebugTimerInterrupt (TRUE);
93
1d5d0ae9 94 // Now we've got UART, make the check:
95 // - The Vector table must be 32-byte aligned
96 ASSERT(((UINT32)SecVectorTable & ((1 << 5)-1)) == 0);
97 }
98
99 // Invalidate the data cache. Doesn't have to do the Data cache clean.
100 ArmInvalidateDataCache();
101
102 //Invalidate Instruction Cache
103 ArmInvalidateInstructionCache();
104
105 //Invalidate I & D TLBs
106 ArmInvalidateInstructionAndDataTlb();
107
108 // Enable Full Access to CoProcessors
109 ArmWriteCPACR (CPACR_CP_FULL_ACCESS);
110
111 // Enable SWP instructions
112 ArmEnableSWPInstruction();
113
114 // Enable program flow prediction, if supported.
115 ArmEnableBranchPrediction();
116
117 if (FixedPcdGet32(PcdVFPEnabled)) {
118 ArmEnableVFP();
119 }
120
0620eec9 121 if (CoreId == ARM_PRIMARY_CORE) {
8e06b586 122 // Initialize peripherals that must be done at the early stage
123 // Example: Some L2x0 controllers must be initialized in Secure World
aa01abaa 124 ArmPlatformSecInitialize ();
1d5d0ae9 125
126 // If we skip the PEI Core we could want to initialize the DRAM in the SEC phase.
127 // If we are in standalone, we need the initialization to copy the UEFI firmware into DRAM
a6caee65 128 if (FeaturePcdGet(PcdSystemMemoryInitializeInSec)) {
1d5d0ae9 129 // Initialize system memory (DRAM)
1ad14bc8 130 ArmPlatformInitializeSystemMemory ();
1d5d0ae9 131 }
132
0620eec9 133 // Some platform can change their physical memory mapping
1ad14bc8 134 ArmPlatformBootRemapping ();
1d5d0ae9 135 }
136
137 // Test if Trustzone is supported on this platform
138 if (ArmPlatformTrustzoneSupported()) {
139 if (FixedPcdGet32(PcdMPCoreSupport)) {
140 // Setup SMP in Non Secure world
1ad14bc8 141 ArmSetupSmpNonSecure (CoreId);
1d5d0ae9 142 }
143
144 // Enter Monitor Mode
145 enter_monitor_mode((VOID*)(PcdGet32(PcdCPUCoresSecMonStackBase) + (PcdGet32(PcdCPUCoreSecMonStackSize) * CoreId)));
146
147 //Write the monitor mode vector table address
148 ArmWriteVMBar((UINT32) &monitor_vector_table);
149
150 //-------------------- Monitor Mode ---------------------
0620eec9 151 // Setup the Trustzone Chipsets
152 if (CoreId == ARM_PRIMARY_CORE) {
1d5d0ae9 153 ArmPlatformTrustzoneInit();
154
155 // Wake up the secondary cores by sending a interrupt to everyone else
156 // NOTE 1: The Software Generated Interrupts are always enabled on Cortex-A9
157 // MPcore test chip on Versatile Express board, So the Software doesn't have to
158 // enable SGI's explicitly.
159 // 2: As no other Interrupts are enabled, doesn't have to worry about the priority.
160 // 3: As all the cores are in secure state, use secure SGI's
161 //
162
55a0d64b 163 ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
164 ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
1d5d0ae9 165
166 // Send SGI to all Secondary core to wake them up from WFI state.
55a0d64b 167 ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
1d5d0ae9 168 } else {
169 // The secondary cores need to wait until the Trustzone chipsets configuration is done
0620eec9 170 // before switching to Non Secure World
1d5d0ae9 171
172 // Enabled GIC CPU Interface
55a0d64b 173 ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
1d5d0ae9 174
175 // Waiting for the SGI from the primary core
176 ArmCallWFI();
177
0620eec9 178 // Acknowledge the interrupt and send End of Interrupt signal.
55a0d64b 179 ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);
1d5d0ae9 180 }
181
182 // Transfer the interrupt to Non-secure World
55a0d64b 183 ArmGicSetupNonSecure (PcdGet32(PcdGicDistributorBase),PcdGet32(PcdGicInterruptInterfaceBase));
1d5d0ae9 184
185 // Write to CP15 Non-secure Access Control Register :
186 // - Enable CP10 and CP11 accesses in NS World
187 // - Enable Access to Preload Engine in NS World
188 // - Enable lockable TLB entries allocation in NS world
189 // - Enable R/W access to SMP bit of Auxiliary Control Register in NS world
190 ArmWriteNsacr(NSACR_NS_SMP | NSACR_TL | NSACR_PLE | NSACR_CP(10) | NSACR_CP(11));
191
192 // CP15 Secure Configuration Register with Non Secure bit (SCR_NS), CPSR.A modified in any
193 // security state (SCR_AW), CPSR.F modified in any security state (SCR_FW)
194 ArmWriteScr(SCR_NS | SCR_FW | SCR_AW);
195 } else {
0620eec9 196 if (CoreId == ARM_PRIMARY_CORE) {
2637d1ef 197 SerialPrint ("Trust Zone Configuration is disabled\n\r");
1d5d0ae9 198 }
199
0620eec9 200 // Trustzone is not enabled, just enable the Distributor and CPU interface
bf7d7a67 201 if (CoreId == ARM_PRIMARY_CORE) {
55a0d64b 202 ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
bf7d7a67 203 }
55a0d64b 204 ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
1d5d0ae9 205
206 // With Trustzone support the transition from Sec to Normal world is done by return_from_exception().
207 // If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program
208 // Status Register as the the current one (CPSR).
a6caee65 209 copy_cpsr_into_spsr ();
1d5d0ae9 210 }
211
a6caee65 212 JumpAddress = PcdGet32 (PcdNormalFvBaseAddress);
213 ArmPlatformSecExtraAction (CoreId, &JumpAddress);
64e03133 214
a6caee65 215 return_from_exception (JumpAddress);
1d5d0ae9 216 //-------------------- Non Secure Mode ---------------------
217
218 // PEI Core should always load and never return
219 ASSERT (FALSE);
220}
221
2637d1ef 222VOID
223SecCommonExceptionEntry (
224 IN UINT32 Entry,
225 IN UINT32 LR
226 )
227{
228 CHAR8 Buffer[100];
229 UINTN CharCount;
230
1d5d0ae9 231 switch (Entry) {
232 case 0:
2637d1ef 233 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reset Exception at 0x%X\n\r",LR);
1d5d0ae9 234 break;
235 case 1:
2637d1ef 236 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Undefined Exception at 0x%X\n\r",LR);
1d5d0ae9 237 break;
238 case 2:
2637d1ef 239 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"SWI Exception at 0x%X\n\r",LR);
1d5d0ae9 240 break;
241 case 3:
2637d1ef 242 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"PrefetchAbort Exception at 0x%X\n\r",LR);
1d5d0ae9 243 break;
244 case 4:
2637d1ef 245 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"DataAbort Exception at 0x%X\n\r",LR);
1d5d0ae9 246 break;
247 case 5:
2637d1ef 248 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reserved Exception at 0x%X\n\r",LR);
1d5d0ae9 249 break;
250 case 6:
2637d1ef 251 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"IRQ Exception at 0x%X\n\r",LR);
1d5d0ae9 252 break;
253 case 7:
2637d1ef 254 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"FIQ Exception at 0x%X\n\r",LR);
1d5d0ae9 255 break;
256 default:
2637d1ef 257 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Unknown Exception at 0x%X\n\r",LR);
1d5d0ae9 258 break;
259 }
2637d1ef 260 SerialPortWrite ((UINT8 *) Buffer, CharCount);
1d5d0ae9 261 while(1);
262}