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1d5d0ae9 | 1 | /** @file |
009f583f | 2 | * Main file supporting the SEC Phase on ARM Platforms |
1d5d0ae9 | 3 | * |
4 | * Copyright (c) 2011, ARM Limited. All rights reserved. | |
5 | * | |
6 | * This program and the accompanying materials | |
7 | * are licensed and made available under the terms and conditions of the BSD License | |
8 | * which accompanies this distribution. The full text of the license may be found at | |
9 | * http://opensource.org/licenses/bsd-license.php | |
10 | * | |
11 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
12 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
13 | * | |
14 | **/ | |
15 | ||
a6caee65 | 16 | #include <Library/DebugAgentLib.h> |
2637d1ef | 17 | #include <Library/PrintLib.h> |
1d5d0ae9 | 18 | #include <Library/BaseMemoryLib.h> |
1d5d0ae9 | 19 | #include <Library/SerialPortLib.h> |
55a0d64b | 20 | #include <Library/ArmGicLib.h> |
90d6a1bb | 21 | #include <Library/ArmCpuLib.h> |
0620eec9 | 22 | |
009f583f | 23 | #include "SecInternal.h" |
24 | ||
e862cd50 | 25 | #define SerialPrint(txt) SerialPortWrite ((UINT8*)txt, AsciiStrLen(txt)+1); |
2637d1ef | 26 | |
1d5d0ae9 | 27 | extern VOID *monitor_vector_table; |
28 | ||
1d5d0ae9 | 29 | VOID |
30 | CEntryPoint ( | |
0787bc61 | 31 | IN UINTN MpId |
1d5d0ae9 | 32 | ) |
33 | { | |
2637d1ef | 34 | CHAR8 Buffer[100]; |
35 | UINTN CharCount; | |
a6caee65 | 36 | UINTN JumpAddress; |
2637d1ef | 37 | |
1d5d0ae9 | 38 | // Primary CPU clears out the SCU tag RAMs, secondaries wait |
0787bc61 | 39 | if (IS_PRIMARY_CORE(MpId)) { |
90d6a1bb | 40 | ArmCpuSetup (MpId); |
41 | ||
42 | if (ArmIsMpCore()) { | |
43 | ArmCpuSynchronizeSignal (ARM_CPU_EVENT_BOOT_MEM_INIT); | |
1d5d0ae9 | 44 | } |
45 | ||
46 | // SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib | |
47 | // In non SEC modules the init call is in autogenerated code. | |
48 | SerialPortInitialize (); | |
2637d1ef | 49 | |
1d5d0ae9 | 50 | // Start talking |
2637d1ef | 51 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"UEFI firmware built at %a on %a\n\r",__TIME__, __DATE__); |
52 | SerialPortWrite ((UINT8 *) Buffer, CharCount); | |
1d5d0ae9 | 53 | |
a6caee65 | 54 | // Initialize the Debug Agent for Source Level Debugging |
55 | InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL); | |
56 | SaveAndSetDebugTimerInterrupt (TRUE); | |
57 | ||
1d5d0ae9 | 58 | // Now we've got UART, make the check: |
59 | // - The Vector table must be 32-byte aligned | |
60 | ASSERT(((UINT32)SecVectorTable & ((1 << 5)-1)) == 0); | |
90d6a1bb | 61 | |
62 | // Enable the GIC distributor and CPU Interface | |
63 | // - no other Interrupts are enabled, doesn't have to worry about the priority. | |
64 | // - all the cores are in secure state, use secure SGI's | |
65 | ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase)); | |
66 | ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase)); | |
67 | } else { | |
68 | // Enable the GIC CPU Interface | |
69 | ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase)); | |
1d5d0ae9 | 70 | } |
71 | ||
72 | // Invalidate the data cache. Doesn't have to do the Data cache clean. | |
73 | ArmInvalidateDataCache(); | |
74 | ||
009f583f | 75 | // Invalidate Instruction Cache |
1d5d0ae9 | 76 | ArmInvalidateInstructionCache(); |
77 | ||
009f583f | 78 | // Invalidate I & D TLBs |
1d5d0ae9 | 79 | ArmInvalidateInstructionAndDataTlb(); |
80 | ||
81 | // Enable Full Access to CoProcessors | |
82 | ArmWriteCPACR (CPACR_CP_FULL_ACCESS); | |
83 | ||
90d6a1bb | 84 | if (FixedPcdGet32 (PcdVFPEnabled)) { |
1d5d0ae9 | 85 | ArmEnableVFP(); |
86 | } | |
87 | ||
0787bc61 | 88 | if (IS_PRIMARY_CORE(MpId)) { |
8e06b586 | 89 | // Initialize peripherals that must be done at the early stage |
90 | // Example: Some L2x0 controllers must be initialized in Secure World | |
aa01abaa | 91 | ArmPlatformSecInitialize (); |
1d5d0ae9 | 92 | |
93 | // If we skip the PEI Core we could want to initialize the DRAM in the SEC phase. | |
94 | // If we are in standalone, we need the initialization to copy the UEFI firmware into DRAM | |
90d6a1bb | 95 | if (FeaturePcdGet (PcdSystemMemoryInitializeInSec)) { |
1d5d0ae9 | 96 | // Initialize system memory (DRAM) |
1ad14bc8 | 97 | ArmPlatformInitializeSystemMemory (); |
1d5d0ae9 | 98 | } |
1d5d0ae9 | 99 | } |
100 | ||
101 | // Test if Trustzone is supported on this platform | |
12c5ae23 | 102 | if (FixedPcdGetBool (PcdTrustzoneSupport)) { |
009f583f | 103 | // Ensure the Monitor Stack Base & Size have been set |
104 | ASSERT(PcdGet32(PcdCPUCoresSecMonStackBase) != 0); | |
105 | ASSERT(PcdGet32(PcdCPUCoreSecMonStackSize) != 0); | |
106 | ||
90d6a1bb | 107 | if (ArmIsMpCore()) { |
1d5d0ae9 | 108 | // Setup SMP in Non Secure world |
90d6a1bb | 109 | ArmCpuSetupSmpNonSecure (GET_CORE_ID(MpId)); |
1d5d0ae9 | 110 | } |
111 | ||
112 | // Enter Monitor Mode | |
0787bc61 | 113 | enter_monitor_mode ((VOID*)(PcdGet32(PcdCPUCoresSecMonStackBase) + (PcdGet32(PcdCPUCoreSecMonStackSize) * GET_CORE_POS(MpId)))); |
1d5d0ae9 | 114 | |
115 | //Write the monitor mode vector table address | |
116 | ArmWriteVMBar((UINT32) &monitor_vector_table); | |
117 | ||
118 | //-------------------- Monitor Mode --------------------- | |
0620eec9 | 119 | // Setup the Trustzone Chipsets |
0787bc61 | 120 | if (IS_PRIMARY_CORE(MpId)) { |
009f583f | 121 | ArmPlatformTrustzoneInit (); |
1d5d0ae9 | 122 | |
90d6a1bb | 123 | // Waiting for the Primary Core to have finished to initialize the Secure World |
124 | ArmCpuSynchronizeSignal (ARM_CPU_EVENT_SECURE_INIT); | |
1d5d0ae9 | 125 | } else { |
126 | // The secondary cores need to wait until the Trustzone chipsets configuration is done | |
0620eec9 | 127 | // before switching to Non Secure World |
1d5d0ae9 | 128 | |
90d6a1bb | 129 | // Waiting for the Primary Core to have finished to initialize the Secure World |
130 | ArmCpuSynchronizeWait (ARM_CPU_EVENT_SECURE_INIT); | |
1d5d0ae9 | 131 | } |
132 | ||
133 | // Transfer the interrupt to Non-secure World | |
90d6a1bb | 134 | ArmGicSetupNonSecure (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase)); |
1d5d0ae9 | 135 | |
136 | // Write to CP15 Non-secure Access Control Register : | |
137 | // - Enable CP10 and CP11 accesses in NS World | |
138 | // - Enable Access to Preload Engine in NS World | |
139 | // - Enable lockable TLB entries allocation in NS world | |
140 | // - Enable R/W access to SMP bit of Auxiliary Control Register in NS world | |
009f583f | 141 | ArmWriteNsacr (NSACR_NS_SMP | NSACR_TL | NSACR_PLE | NSACR_CP(10) | NSACR_CP(11)); |
1d5d0ae9 | 142 | |
143 | // CP15 Secure Configuration Register with Non Secure bit (SCR_NS), CPSR.A modified in any | |
144 | // security state (SCR_AW), CPSR.F modified in any security state (SCR_FW) | |
009f583f | 145 | ArmWriteScr (SCR_NS | SCR_FW | SCR_AW); |
1d5d0ae9 | 146 | } else { |
0787bc61 | 147 | if (IS_PRIMARY_CORE(MpId)) { |
2637d1ef | 148 | SerialPrint ("Trust Zone Configuration is disabled\n\r"); |
1d5d0ae9 | 149 | } |
150 | ||
1d5d0ae9 | 151 | // With Trustzone support the transition from Sec to Normal world is done by return_from_exception(). |
152 | // If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program | |
153 | // Status Register as the the current one (CPSR). | |
a6caee65 | 154 | copy_cpsr_into_spsr (); |
1d5d0ae9 | 155 | } |
156 | ||
f92b93c9 | 157 | JumpAddress = PcdGet32 (PcdFvBaseAddress); |
0787bc61 | 158 | ArmPlatformSecExtraAction (MpId, &JumpAddress); |
64e03133 | 159 | |
a6caee65 | 160 | return_from_exception (JumpAddress); |
1d5d0ae9 | 161 | //-------------------- Non Secure Mode --------------------- |
162 | ||
163 | // PEI Core should always load and never return | |
164 | ASSERT (FALSE); | |
165 | } | |
166 | ||
2637d1ef | 167 | VOID |
168 | SecCommonExceptionEntry ( | |
169 | IN UINT32 Entry, | |
170 | IN UINT32 LR | |
171 | ) | |
172 | { | |
173 | CHAR8 Buffer[100]; | |
174 | UINTN CharCount; | |
175 | ||
1d5d0ae9 | 176 | switch (Entry) { |
177 | case 0: | |
2637d1ef | 178 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reset Exception at 0x%X\n\r",LR); |
1d5d0ae9 | 179 | break; |
180 | case 1: | |
2637d1ef | 181 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Undefined Exception at 0x%X\n\r",LR); |
1d5d0ae9 | 182 | break; |
183 | case 2: | |
2637d1ef | 184 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"SWI Exception at 0x%X\n\r",LR); |
1d5d0ae9 | 185 | break; |
186 | case 3: | |
2637d1ef | 187 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"PrefetchAbort Exception at 0x%X\n\r",LR); |
1d5d0ae9 | 188 | break; |
189 | case 4: | |
2637d1ef | 190 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"DataAbort Exception at 0x%X\n\r",LR); |
1d5d0ae9 | 191 | break; |
192 | case 5: | |
2637d1ef | 193 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reserved Exception at 0x%X\n\r",LR); |
1d5d0ae9 | 194 | break; |
195 | case 6: | |
2637d1ef | 196 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"IRQ Exception at 0x%X\n\r",LR); |
1d5d0ae9 | 197 | break; |
198 | case 7: | |
2637d1ef | 199 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"FIQ Exception at 0x%X\n\r",LR); |
1d5d0ae9 | 200 | break; |
201 | default: | |
2637d1ef | 202 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Unknown Exception at 0x%X\n\r",LR); |
1d5d0ae9 | 203 | break; |
204 | } | |
2637d1ef | 205 | SerialPortWrite ((UINT8 *) Buffer, CharCount); |
1d5d0ae9 | 206 | while(1); |
207 | } |