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1d5d0ae9 | 1 | /** @file |
009f583f | 2 | * Main file supporting the SEC Phase on ARM Platforms |
1d5d0ae9 | 3 | * |
4 | * Copyright (c) 2011, ARM Limited. All rights reserved. | |
5 | * | |
6 | * This program and the accompanying materials | |
7 | * are licensed and made available under the terms and conditions of the BSD License | |
8 | * which accompanies this distribution. The full text of the license may be found at | |
9 | * http://opensource.org/licenses/bsd-license.php | |
10 | * | |
11 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
12 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
13 | * | |
14 | **/ | |
15 | ||
a6caee65 | 16 | #include <Library/DebugAgentLib.h> |
2637d1ef | 17 | #include <Library/PrintLib.h> |
1d5d0ae9 | 18 | #include <Library/BaseMemoryLib.h> |
1d5d0ae9 | 19 | #include <Library/SerialPortLib.h> |
55a0d64b | 20 | #include <Library/ArmGicLib.h> |
90d6a1bb | 21 | #include <Library/ArmCpuLib.h> |
0620eec9 | 22 | |
009f583f | 23 | #include "SecInternal.h" |
24 | ||
e862cd50 | 25 | #define SerialPrint(txt) SerialPortWrite ((UINT8*)txt, AsciiStrLen(txt)+1); |
2637d1ef | 26 | |
1d5d0ae9 | 27 | extern VOID *monitor_vector_table; |
28 | ||
1d5d0ae9 | 29 | VOID |
30 | CEntryPoint ( | |
0787bc61 | 31 | IN UINTN MpId |
1d5d0ae9 | 32 | ) |
33 | { | |
2637d1ef | 34 | CHAR8 Buffer[100]; |
35 | UINTN CharCount; | |
a6caee65 | 36 | UINTN JumpAddress; |
2637d1ef | 37 | |
710b8acb | 38 | // Invalidate the data cache. Doesn't have to do the Data cache clean. |
39 | ArmInvalidateDataCache(); | |
40 | ||
41 | // Invalidate Instruction Cache | |
42 | ArmInvalidateInstructionCache(); | |
43 | ||
44 | // Invalidate I & D TLBs | |
45 | ArmInvalidateInstructionAndDataTlb(); | |
46 | ||
47 | // CPU specific settings | |
48 | ArmCpuSetup (MpId); | |
49 | ||
1d5d0ae9 | 50 | // Primary CPU clears out the SCU tag RAMs, secondaries wait |
0787bc61 | 51 | if (IS_PRIMARY_CORE(MpId)) { |
90d6a1bb | 52 | if (ArmIsMpCore()) { |
53 | ArmCpuSynchronizeSignal (ARM_CPU_EVENT_BOOT_MEM_INIT); | |
1d5d0ae9 | 54 | } |
55 | ||
56 | // SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib | |
57 | // In non SEC modules the init call is in autogenerated code. | |
58 | SerialPortInitialize (); | |
2637d1ef | 59 | |
1d5d0ae9 | 60 | // Start talking |
2637d1ef | 61 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"UEFI firmware built at %a on %a\n\r",__TIME__, __DATE__); |
62 | SerialPortWrite ((UINT8 *) Buffer, CharCount); | |
1d5d0ae9 | 63 | |
a6caee65 | 64 | // Initialize the Debug Agent for Source Level Debugging |
65 | InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL); | |
66 | SaveAndSetDebugTimerInterrupt (TRUE); | |
67 | ||
1d5d0ae9 | 68 | // Now we've got UART, make the check: |
69 | // - The Vector table must be 32-byte aligned | |
70 | ASSERT(((UINT32)SecVectorTable & ((1 << 5)-1)) == 0); | |
90d6a1bb | 71 | |
72 | // Enable the GIC distributor and CPU Interface | |
73 | // - no other Interrupts are enabled, doesn't have to worry about the priority. | |
74 | // - all the cores are in secure state, use secure SGI's | |
75 | ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase)); | |
76 | ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase)); | |
77 | } else { | |
78 | // Enable the GIC CPU Interface | |
79 | ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase)); | |
1d5d0ae9 | 80 | } |
81 | ||
1d5d0ae9 | 82 | // Enable Full Access to CoProcessors |
83 | ArmWriteCPACR (CPACR_CP_FULL_ACCESS); | |
84 | ||
90d6a1bb | 85 | if (FixedPcdGet32 (PcdVFPEnabled)) { |
1d5d0ae9 | 86 | ArmEnableVFP(); |
87 | } | |
88 | ||
0787bc61 | 89 | if (IS_PRIMARY_CORE(MpId)) { |
8e06b586 | 90 | // Initialize peripherals that must be done at the early stage |
91 | // Example: Some L2x0 controllers must be initialized in Secure World | |
aa01abaa | 92 | ArmPlatformSecInitialize (); |
1d5d0ae9 | 93 | |
94 | // If we skip the PEI Core we could want to initialize the DRAM in the SEC phase. | |
95 | // If we are in standalone, we need the initialization to copy the UEFI firmware into DRAM | |
90d6a1bb | 96 | if (FeaturePcdGet (PcdSystemMemoryInitializeInSec)) { |
1d5d0ae9 | 97 | // Initialize system memory (DRAM) |
1ad14bc8 | 98 | ArmPlatformInitializeSystemMemory (); |
1d5d0ae9 | 99 | } |
1d5d0ae9 | 100 | } |
101 | ||
102 | // Test if Trustzone is supported on this platform | |
12c5ae23 | 103 | if (FixedPcdGetBool (PcdTrustzoneSupport)) { |
009f583f | 104 | // Ensure the Monitor Stack Base & Size have been set |
105 | ASSERT(PcdGet32(PcdCPUCoresSecMonStackBase) != 0); | |
106 | ASSERT(PcdGet32(PcdCPUCoreSecMonStackSize) != 0); | |
107 | ||
90d6a1bb | 108 | if (ArmIsMpCore()) { |
1d5d0ae9 | 109 | // Setup SMP in Non Secure world |
90d6a1bb | 110 | ArmCpuSetupSmpNonSecure (GET_CORE_ID(MpId)); |
1d5d0ae9 | 111 | } |
112 | ||
113 | // Enter Monitor Mode | |
0787bc61 | 114 | enter_monitor_mode ((VOID*)(PcdGet32(PcdCPUCoresSecMonStackBase) + (PcdGet32(PcdCPUCoreSecMonStackSize) * GET_CORE_POS(MpId)))); |
1d5d0ae9 | 115 | |
116 | //Write the monitor mode vector table address | |
117 | ArmWriteVMBar((UINT32) &monitor_vector_table); | |
118 | ||
119 | //-------------------- Monitor Mode --------------------- | |
0620eec9 | 120 | // Setup the Trustzone Chipsets |
0787bc61 | 121 | if (IS_PRIMARY_CORE(MpId)) { |
009f583f | 122 | ArmPlatformTrustzoneInit (); |
1d5d0ae9 | 123 | |
90d6a1bb | 124 | // Waiting for the Primary Core to have finished to initialize the Secure World |
125 | ArmCpuSynchronizeSignal (ARM_CPU_EVENT_SECURE_INIT); | |
1d5d0ae9 | 126 | } else { |
127 | // The secondary cores need to wait until the Trustzone chipsets configuration is done | |
0620eec9 | 128 | // before switching to Non Secure World |
1d5d0ae9 | 129 | |
90d6a1bb | 130 | // Waiting for the Primary Core to have finished to initialize the Secure World |
131 | ArmCpuSynchronizeWait (ARM_CPU_EVENT_SECURE_INIT); | |
1d5d0ae9 | 132 | } |
133 | ||
134 | // Transfer the interrupt to Non-secure World | |
90d6a1bb | 135 | ArmGicSetupNonSecure (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase)); |
1d5d0ae9 | 136 | |
513aa349 | 137 | // Write to CP15 Non-secure Access Control Register |
138 | ArmWriteNsacr (PcdGet32 (PcdArmNsacr)); | |
139 | ||
140 | // CP15 Secure Configuration Register | |
141 | ArmWriteScr (PcdGet32 (PcdArmScr)); | |
1d5d0ae9 | 142 | } else { |
0787bc61 | 143 | if (IS_PRIMARY_CORE(MpId)) { |
2637d1ef | 144 | SerialPrint ("Trust Zone Configuration is disabled\n\r"); |
1d5d0ae9 | 145 | } |
146 | ||
1d5d0ae9 | 147 | // With Trustzone support the transition from Sec to Normal world is done by return_from_exception(). |
148 | // If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program | |
149 | // Status Register as the the current one (CPSR). | |
a6caee65 | 150 | copy_cpsr_into_spsr (); |
1d5d0ae9 | 151 | } |
152 | ||
f92b93c9 | 153 | JumpAddress = PcdGet32 (PcdFvBaseAddress); |
0787bc61 | 154 | ArmPlatformSecExtraAction (MpId, &JumpAddress); |
64e03133 | 155 | |
513aa349 | 156 | // If PcdArmNonSecModeTransition is defined then set this specific mode to CPSR before the transition |
157 | // By not set, the mode for Non Secure World is SVC | |
158 | if (PcdGet32 (PcdArmNonSecModeTransition) != 0) { | |
159 | set_non_secure_mode ((ARM_PROCESSOR_MODE)PcdGet32 (PcdArmNonSecModeTransition)); | |
160 | } | |
161 | ||
a6caee65 | 162 | return_from_exception (JumpAddress); |
1d5d0ae9 | 163 | //-------------------- Non Secure Mode --------------------- |
164 | ||
165 | // PEI Core should always load and never return | |
166 | ASSERT (FALSE); | |
167 | } | |
168 | ||
2637d1ef | 169 | VOID |
170 | SecCommonExceptionEntry ( | |
171 | IN UINT32 Entry, | |
172 | IN UINT32 LR | |
173 | ) | |
174 | { | |
175 | CHAR8 Buffer[100]; | |
176 | UINTN CharCount; | |
177 | ||
1d5d0ae9 | 178 | switch (Entry) { |
179 | case 0: | |
2637d1ef | 180 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reset Exception at 0x%X\n\r",LR); |
1d5d0ae9 | 181 | break; |
182 | case 1: | |
2637d1ef | 183 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Undefined Exception at 0x%X\n\r",LR); |
1d5d0ae9 | 184 | break; |
185 | case 2: | |
2637d1ef | 186 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"SWI Exception at 0x%X\n\r",LR); |
1d5d0ae9 | 187 | break; |
188 | case 3: | |
2637d1ef | 189 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"PrefetchAbort Exception at 0x%X\n\r",LR); |
1d5d0ae9 | 190 | break; |
191 | case 4: | |
2637d1ef | 192 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"DataAbort Exception at 0x%X\n\r",LR); |
1d5d0ae9 | 193 | break; |
194 | case 5: | |
2637d1ef | 195 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reserved Exception at 0x%X\n\r",LR); |
1d5d0ae9 | 196 | break; |
197 | case 6: | |
2637d1ef | 198 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"IRQ Exception at 0x%X\n\r",LR); |
1d5d0ae9 | 199 | break; |
200 | case 7: | |
2637d1ef | 201 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"FIQ Exception at 0x%X\n\r",LR); |
1d5d0ae9 | 202 | break; |
203 | default: | |
2637d1ef | 204 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Unknown Exception at 0x%X\n\r",LR); |
1d5d0ae9 | 205 | break; |
206 | } | |
2637d1ef | 207 | SerialPortWrite ((UINT8 *) Buffer, CharCount); |
1d5d0ae9 | 208 | while(1); |
209 | } |