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1 | /** @file |
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2 | * Main file supporting the SEC Phase on ARM Platforms |
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3 | * |
4 | * Copyright (c) 2011, ARM Limited. All rights reserved. |
5 | * |
6 | * This program and the accompanying materials |
7 | * are licensed and made available under the terms and conditions of the BSD License |
8 | * which accompanies this distribution. The full text of the license may be found at |
9 | * http://opensource.org/licenses/bsd-license.php |
10 | * |
11 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, |
12 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. |
13 | * |
14 | **/ |
15 | |
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16 | #include <Library/DebugAgentLib.h> |
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17 | #include <Library/PrintLib.h> |
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18 | #include <Library/BaseMemoryLib.h> |
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19 | #include <Library/SerialPortLib.h> |
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20 | #include <Library/ArmGicLib.h> |
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21 | #include <Library/ArmCpuLib.h> |
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22 | |
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23 | #include "SecInternal.h" |
24 | |
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25 | #define SerialPrint(txt) SerialPortWrite ((UINT8*)txt, AsciiStrLen(txt)+1); |
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26 | |
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27 | extern VOID *monitor_vector_table; |
28 | |
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29 | VOID |
30 | CEntryPoint ( |
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31 | IN UINTN MpId |
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32 | ) |
33 | { |
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34 | CHAR8 Buffer[100]; |
35 | UINTN CharCount; |
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36 | UINTN JumpAddress; |
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37 | |
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38 | // Invalidate the data cache. Doesn't have to do the Data cache clean. |
39 | ArmInvalidateDataCache(); |
40 | |
41 | // Invalidate Instruction Cache |
42 | ArmInvalidateInstructionCache(); |
43 | |
44 | // Invalidate I & D TLBs |
45 | ArmInvalidateInstructionAndDataTlb(); |
46 | |
47 | // CPU specific settings |
48 | ArmCpuSetup (MpId); |
49 | |
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50 | // Enable Floating Point Coprocessor if supported by the platform |
51 | if (FixedPcdGet32 (PcdVFPEnabled)) { |
52 | ArmEnableVFP(); |
53 | } |
54 | |
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55 | // Primary CPU clears out the SCU tag RAMs, secondaries wait |
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56 | if (IS_PRIMARY_CORE(MpId)) { |
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57 | if (ArmIsMpCore()) { |
58 | ArmCpuSynchronizeSignal (ARM_CPU_EVENT_BOOT_MEM_INIT); |
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59 | } |
60 | |
61 | // SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib |
62 | // In non SEC modules the init call is in autogenerated code. |
63 | SerialPortInitialize (); |
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64 | |
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65 | // Start talking |
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66 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"UEFI firmware built at %a on %a\n\r",__TIME__, __DATE__); |
67 | SerialPortWrite ((UINT8 *) Buffer, CharCount); |
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68 | |
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69 | // Initialize the Debug Agent for Source Level Debugging |
70 | InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL); |
71 | SaveAndSetDebugTimerInterrupt (TRUE); |
72 | |
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73 | // Now we've got UART, make the check: |
74 | // - The Vector table must be 32-byte aligned |
75 | ASSERT(((UINT32)SecVectorTable & ((1 << 5)-1)) == 0); |
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76 | |
77 | // Enable the GIC distributor and CPU Interface |
78 | // - no other Interrupts are enabled, doesn't have to worry about the priority. |
79 | // - all the cores are in secure state, use secure SGI's |
80 | ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase)); |
81 | ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase)); |
82 | } else { |
83 | // Enable the GIC CPU Interface |
84 | ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase)); |
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85 | } |
86 | |
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87 | // Enable Full Access to CoProcessors |
88 | ArmWriteCPACR (CPACR_CP_FULL_ACCESS); |
89 | |
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90 | if (IS_PRIMARY_CORE(MpId)) { |
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91 | // Initialize peripherals that must be done at the early stage |
92 | // Example: Some L2x0 controllers must be initialized in Secure World |
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93 | ArmPlatformSecInitialize (); |
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94 | |
95 | // If we skip the PEI Core we could want to initialize the DRAM in the SEC phase. |
96 | // If we are in standalone, we need the initialization to copy the UEFI firmware into DRAM |
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97 | if (FeaturePcdGet (PcdSystemMemoryInitializeInSec)) { |
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98 | // Initialize system memory (DRAM) |
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99 | ArmPlatformInitializeSystemMemory (); |
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100 | } |
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101 | } |
102 | |
103 | // Test if Trustzone is supported on this platform |
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104 | if (FixedPcdGetBool (PcdTrustzoneSupport)) { |
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105 | // Ensure the Monitor Stack Base & Size have been set |
106 | ASSERT(PcdGet32(PcdCPUCoresSecMonStackBase) != 0); |
107 | ASSERT(PcdGet32(PcdCPUCoreSecMonStackSize) != 0); |
108 | |
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109 | if (ArmIsMpCore()) { |
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110 | // Setup SMP in Non Secure world |
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111 | ArmCpuSetupSmpNonSecure (GET_CORE_ID(MpId)); |
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112 | } |
113 | |
114 | // Enter Monitor Mode |
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115 | enter_monitor_mode ((VOID*)(PcdGet32(PcdCPUCoresSecMonStackBase) + (PcdGet32(PcdCPUCoreSecMonStackSize) * GET_CORE_POS(MpId)))); |
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116 | |
117 | //Write the monitor mode vector table address |
118 | ArmWriteVMBar((UINT32) &monitor_vector_table); |
119 | |
120 | //-------------------- Monitor Mode --------------------- |
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121 | // Setup the Trustzone Chipsets |
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122 | if (IS_PRIMARY_CORE(MpId)) { |
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123 | ArmPlatformTrustzoneInit (); |
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124 | |
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125 | // Waiting for the Primary Core to have finished to initialize the Secure World |
126 | ArmCpuSynchronizeSignal (ARM_CPU_EVENT_SECURE_INIT); |
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127 | } else { |
128 | // The secondary cores need to wait until the Trustzone chipsets configuration is done |
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129 | // before switching to Non Secure World |
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130 | |
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131 | // Waiting for the Primary Core to have finished to initialize the Secure World |
132 | ArmCpuSynchronizeWait (ARM_CPU_EVENT_SECURE_INIT); |
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133 | } |
134 | |
135 | // Transfer the interrupt to Non-secure World |
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136 | ArmGicSetupNonSecure (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase)); |
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137 | |
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138 | // Write to CP15 Non-secure Access Control Register |
139 | ArmWriteNsacr (PcdGet32 (PcdArmNsacr)); |
140 | |
141 | // CP15 Secure Configuration Register |
142 | ArmWriteScr (PcdGet32 (PcdArmScr)); |
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143 | } else { |
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144 | if (IS_PRIMARY_CORE(MpId)) { |
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145 | SerialPrint ("Trust Zone Configuration is disabled\n\r"); |
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146 | } |
147 | |
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148 | // With Trustzone support the transition from Sec to Normal world is done by return_from_exception(). |
149 | // If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program |
150 | // Status Register as the the current one (CPSR). |
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151 | copy_cpsr_into_spsr (); |
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152 | } |
153 | |
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154 | JumpAddress = PcdGet32 (PcdFvBaseAddress); |
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155 | ArmPlatformSecExtraAction (MpId, &JumpAddress); |
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156 | |
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157 | // If PcdArmNonSecModeTransition is defined then set this specific mode to CPSR before the transition |
158 | // By not set, the mode for Non Secure World is SVC |
159 | if (PcdGet32 (PcdArmNonSecModeTransition) != 0) { |
160 | set_non_secure_mode ((ARM_PROCESSOR_MODE)PcdGet32 (PcdArmNonSecModeTransition)); |
161 | } |
162 | |
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163 | return_from_exception (JumpAddress); |
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164 | //-------------------- Non Secure Mode --------------------- |
165 | |
166 | // PEI Core should always load and never return |
167 | ASSERT (FALSE); |
168 | } |
169 | |
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170 | VOID |
171 | SecCommonExceptionEntry ( |
172 | IN UINT32 Entry, |
173 | IN UINT32 LR |
174 | ) |
175 | { |
176 | CHAR8 Buffer[100]; |
177 | UINTN CharCount; |
178 | |
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179 | switch (Entry) { |
180 | case 0: |
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181 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reset Exception at 0x%X\n\r",LR); |
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182 | break; |
183 | case 1: |
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184 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Undefined Exception at 0x%X\n\r",LR); |
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185 | break; |
186 | case 2: |
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187 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"SWI Exception at 0x%X\n\r",LR); |
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188 | break; |
189 | case 3: |
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190 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"PrefetchAbort Exception at 0x%X\n\r",LR); |
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191 | break; |
192 | case 4: |
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193 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"DataAbort Exception at 0x%X\n\r",LR); |
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194 | break; |
195 | case 5: |
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196 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reserved Exception at 0x%X\n\r",LR); |
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197 | break; |
198 | case 6: |
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199 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"IRQ Exception at 0x%X\n\r",LR); |
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200 | break; |
201 | case 7: |
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202 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"FIQ Exception at 0x%X\n\r",LR); |
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203 | break; |
204 | default: |
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205 | CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Unknown Exception at 0x%X\n\r",LR); |
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206 | break; |
207 | } |
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208 | SerialPortWrite ((UINT8 *) Buffer, CharCount); |
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209 | while(1); |
210 | } |