]>
Commit | Line | Data |
---|---|---|
11c20f4e | 1 | #------------------------------------------------------------------------------ \r |
2 | #\r | |
3 | # ARM VE Entry point. Reset vector in FV header will brach to\r | |
4 | # _ModuleEntryPoint. \r | |
5 | #\r | |
6 | # Copyright (c) 2011, ARM Limited. All rights reserved.\r | |
7 | # \r | |
8 | # This program and the accompanying materials \r | |
9 | # are licensed and made available under the terms and conditions of the BSD License \r | |
10 | # which accompanies this distribution. The full text of the license may be found at \r | |
11 | # http://opensource.org/licenses/bsd-license.php \r | |
12 | #\r | |
13 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
14 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
15 | #\r | |
16 | #------------------------------------------------------------------------------\r | |
17 | \r | |
18 | #include <AsmMacroIoLib.h>\r | |
19 | #include <Base.h>\r | |
20 | #include <Library/PcdLib.h>\r | |
21 | #include <Library/ArmPlatformLib.h>\r | |
22 | #include <AutoGen.h>\r | |
23 | \r | |
24 | #Start of Code section\r | |
25 | .text\r | |
26 | .align 3\r | |
27 | \r | |
28 | #make _ModuleEntryPoint as global\r | |
29 | GCC_ASM_EXPORT(_ModuleEntryPoint)\r | |
30 | \r | |
31 | #global functions referenced by this module\r | |
32 | GCC_ASM_IMPORT(CEntryPoint)\r | |
44e272fd | 33 | GCC_ASM_IMPORT(ArmPlatformSecBootAction)\r |
11c20f4e | 34 | GCC_ASM_IMPORT(ArmPlatformInitializeBootMemory)\r |
35 | GCC_ASM_IMPORT(ArmDisableInterrupts)\r | |
36 | GCC_ASM_IMPORT(ArmDisableCachesAndMmu)\r | |
37 | GCC_ASM_IMPORT(ArmWriteVBar)\r | |
0787bc61 | 38 | GCC_ASM_IMPORT(ArmReadMpidr)\r |
11c20f4e | 39 | GCC_ASM_IMPORT(SecVectorTable)\r |
40 | \r | |
41 | #if (FixedPcdGet32(PcdMPCoreSupport))\r | |
42 | GCC_ASM_IMPORT(ArmIsScuEnable)\r | |
43 | #endif\r | |
44 | \r | |
45 | StartupAddr: .word ASM_PFX(CEntryPoint)\r | |
46 | SecVectorTableAddr: .word ASM_PFX(SecVectorTable)\r | |
47 | \r | |
48 | ASM_PFX(_ModuleEntryPoint):\r | |
11c20f4e | 49 | # First ensure all interrupts are disabled\r |
50 | bl ASM_PFX(ArmDisableInterrupts)\r | |
51 | \r | |
52 | # Ensure that the MMU and caches are off\r | |
53 | bl ASM_PFX(ArmDisableCachesAndMmu)\r | |
54 | \r | |
44e272fd | 55 | # Jump to Platform Specific Boot Action function\r |
56 | blx ASM_PFX(ArmPlatformSecBootAction)\r | |
57 | \r | |
58 | # Set VBAR to the start of the exception vectors in Secure Mode\r | |
59 | ldr r0, =SecVectorTable\r | |
60 | bl ASM_PFX(ArmWriteVBar)\r | |
61 | \r | |
11c20f4e | 62 | _IdentifyCpu: \r |
63 | # Identify CPU ID\r | |
64 | bl ASM_PFX(ArmReadMpidr)\r | |
0787bc61 | 65 | // Get ID of this CPU in Multicore system\r |
66 | LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r | |
67 | and r5, r0, r1\r | |
11c20f4e | 68 | \r |
69 | #get ID of this CPU in Multicore system\r | |
0787bc61 | 70 | LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r1)\r |
71 | cmp r5, r1\r | |
11c20f4e | 72 | # Only the primary core initialize the memory (SMC)\r |
73 | beq _InitMem\r | |
74 | \r | |
75 | #if (FixedPcdGet32(PcdMPCoreSupport))\r | |
76 | # ... The secondary cores wait for SCU to be enabled\r | |
77 | _WaitForEnabledScu:\r | |
78 | bl ASM_PFX(ArmIsScuEnable)\r | |
79 | tst r1, #1\r | |
80 | beq _WaitForEnabledScu\r | |
81 | b _SetupStack\r | |
82 | #endif\r | |
83 | \r | |
84 | _InitMem:\r | |
f156d5b4 | 85 | // Initialize Init Boot Memory\r |
11c20f4e | 86 | bl ASM_PFX(ArmPlatformInitializeBootMemory)\r |
87 | \r | |
88 | # Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)\r | |
89 | mov r5, #0\r | |
90 | \r | |
91 | _SetupStack:\r | |
92 | # Setup Stack for the 4 CPU cores\r | |
93 | #Read Stack Base address from PCD\r | |
94 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r | |
95 | \r | |
96 | #read Stack size from PCD\r | |
97 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecStackSize), r2)\r | |
98 | \r | |
99 | #calcuate Stack Pointer reg value using Stack size and CPU ID.\r | |
100 | mov r3,r5 @ r3 = core_id\r | |
101 | mul r3,r3,r2 @ r3 = core_id * stack_size = offset from the stack base\r | |
102 | add r3,r3,r1 @ r3 ldr= stack_base + offset\r | |
103 | mov sp, r3\r | |
104 | \r | |
105 | # move sec startup address into a data register\r | |
106 | # ensure we're jumping to FV version of the code (not boot remapped alias)\r | |
107 | ldr r3, StartupAddr\r | |
108 | \r | |
109 | # Move the CoreId in r0 to be the first argument of the SEC Entry Point\r | |
110 | mov r0, r5\r | |
111 | \r | |
112 | # jump to SEC C code\r | |
113 | # r0 = core_id\r | |
114 | blx r3\r | |
115 | \r | |
116 | \r |