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f7496d71 LG |
1 | /** @file\r |
2 | x64 Long Mode Virtual Memory Management Definitions\r | |
30fdf114 | 3 | \r |
97fa0ee9 YL |
4 | References:\r |
5 | 1) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 1:Basic Architecture, Intel\r | |
6 | 2) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel\r | |
7 | 3) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel\r | |
8 | 4) AMD64 Architecture Programmer's Manual Volume 2: System Programming\r | |
f7496d71 LG |
9 | \r |
10 | Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r | |
11 | This program and the accompanying materials\r | |
12 | are licensed and made available under the terms and conditions of the BSD License\r | |
13 | which accompanies this distribution. The full text of the license may be found at\r | |
14 | http://opensource.org/licenses/bsd-license.php\r | |
15 | \r | |
16 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
17 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
18 | \r | |
30fdf114 LG |
19 | **/\r |
20 | \r | |
21 | #ifndef _VIRTUAL_MEMORY_H_\r | |
22 | #define _VIRTUAL_MEMORY_H_\r | |
23 | \r | |
24 | #include "CommonLib.h"\r | |
25 | \r | |
26 | #pragma pack(1)\r | |
27 | \r | |
28 | //\r | |
29 | // Page-Map Level-4 Offset (PML4) and\r | |
30 | // Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB\r | |
31 | //\r | |
32 | \r | |
33 | typedef union {\r | |
34 | struct {\r | |
35 | UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r | |
36 | UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r | |
37 | UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r | |
38 | UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r | |
39 | UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r | |
40 | UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r | |
41 | UINT64 Reserved:1; // Reserved\r | |
42 | UINT64 MustBeZero:2; // Must Be Zero\r | |
43 | UINT64 Available:3; // Available for use by system software\r | |
44 | UINT64 PageTableBaseAddress:40; // Page Table Base Address\r | |
45 | UINT64 AvabilableHigh:11; // Available for use by system software\r | |
46 | UINT64 Nx:1; // No Execute bit\r | |
47 | } Bits;\r | |
48 | UINT64 Uint64;\r | |
49 | } X64_PAGE_MAP_AND_DIRECTORY_POINTER_2MB_4K;\r | |
50 | \r | |
51 | //\r | |
52 | // Page-Directory Offset 4K\r | |
53 | //\r | |
54 | typedef union {\r | |
55 | struct {\r | |
56 | UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r | |
57 | UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r | |
58 | UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r | |
59 | UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r | |
60 | UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r | |
61 | UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r | |
62 | UINT64 Reserved:1; // Reserved\r | |
63 | UINT64 MustBeZero:1; // Must Be Zero\r | |
64 | UINT64 Reserved2:1; // Reserved\r | |
65 | UINT64 Available:3; // Available for use by system software\r | |
66 | UINT64 PageTableBaseAddress:40; // Page Table Base Address\r | |
67 | UINT64 AvabilableHigh:11; // Available for use by system software\r | |
68 | UINT64 Nx:1; // No Execute bit\r | |
69 | } Bits;\r | |
70 | UINT64 Uint64;\r | |
71 | } X64_PAGE_DIRECTORY_ENTRY_4K;\r | |
72 | \r | |
73 | //\r | |
74 | // Page Table Entry 4K\r | |
75 | //\r | |
76 | typedef union {\r | |
77 | struct {\r | |
78 | UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r | |
79 | UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r | |
80 | UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r | |
81 | UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r | |
82 | UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r | |
83 | UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r | |
84 | UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r | |
f7496d71 | 85 | UINT64 PAT:1; // 0 = Ignore Page Attribute Table\r |
30fdf114 LG |
86 | UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r |
87 | UINT64 Available:3; // Available for use by system software\r | |
88 | UINT64 PageTableBaseAddress:40; // Page Table Base Address\r | |
89 | UINT64 AvabilableHigh:11; // Available for use by system software\r | |
90 | UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r | |
91 | } Bits;\r | |
92 | UINT64 Uint64;\r | |
93 | } X64_PAGE_TABLE_ENTRY_4K;\r | |
94 | \r | |
95 | \r | |
96 | //\r | |
97 | // Page Table Entry 2MB\r | |
98 | //\r | |
99 | typedef union {\r | |
100 | struct {\r | |
101 | UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r | |
102 | UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r | |
103 | UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r | |
104 | UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r | |
105 | UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r | |
106 | UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r | |
107 | UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r | |
f7496d71 | 108 | UINT64 MustBe1:1; // Must be 1\r |
30fdf114 LG |
109 | UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r |
110 | UINT64 Available:3; // Available for use by system software\r | |
111 | UINT64 PAT:1; //\r | |
112 | UINT64 MustBeZero:8; // Must be zero;\r | |
113 | UINT64 PageTableBaseAddress:31; // Page Table Base Address\r | |
114 | UINT64 AvabilableHigh:11; // Available for use by system software\r | |
115 | UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r | |
116 | } Bits;\r | |
117 | UINT64 Uint64;\r | |
118 | } X64_PAGE_TABLE_ENTRY_2M;\r | |
119 | \r | |
120 | #pragma pack()\r | |
121 | \r | |
f7496d71 | 122 | #endif\r |