[mirror_edk2.git] / BeagleBoardPkg / Include / BeagleBoard.h

/** @file\r
*  Header defining the BeagleBoard constants (Base addresses, sizes, flags)\r
*\r
*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
*\r
*  SPDX-License-Identifier: BSD-2-Clause-Patent\r
*\r
**/\r
\r
#ifndef __BEAGLEBOARD_PLATFORM_H__\r
#define __BEAGLEBOARD_PLATFORM_H__\r
\r
// DDR attributes\r
#define DDR_ATTRIBUTES_CACHED                ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r
#define DDR_ATTRIBUTES_UNCACHED              ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED\r
\r
// SoC registers. L3 interconnects\r
#define SOC_REGISTERS_L3_PHYSICAL_BASE       0x68000000\r
#define SOC_REGISTERS_L3_PHYSICAL_LENGTH     0x08000000\r
#define SOC_REGISTERS_L3_ATTRIBUTES          ARM_MEMORY_REGION_ATTRIBUTE_DEVICE\r
\r
// SoC registers. L4 interconnects\r
#define SOC_REGISTERS_L4_PHYSICAL_BASE       0x48000000\r
#define SOC_REGISTERS_L4_PHYSICAL_LENGTH     0x08000000\r
#define SOC_REGISTERS_L4_ATTRIBUTES          ARM_MEMORY_REGION_ATTRIBUTE_DEVICE\r
\r
\r
#if 0\r
/*******************************************\r
// Platform Memory Map\r
*******************************************/\r
\r
// Can be NOR, DOC, DRAM, SRAM\r
#define ARM_EB_REMAP_BASE                     0x00000000\r
#define ARM_EB_REMAP_SZ                       0x04000000\r
\r
// Motherboard Peripheral and On-chip peripheral\r
#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE     0x10000000\r
#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_SZ       0x00100000\r
#define ARM_EB_BOARD_PERIPH_BASE              0x10000000\r
//#define ARM_EB_CHIP_PERIPH_BASE             0x10020000\r
\r
// SMC\r
#define ARM_EB_SMC_BASE                       0x40000000\r
#define ARM_EB_SMC_SZ                         0x20000000\r
\r
// NOR Flash 1\r
#define ARM_EB_SMB_NOR_BASE                   0x40000000\r
#define ARM_EB_SMB_NOR_SZ                     0x04000000 /* 64 MB */\r
// DOC Flash\r
#define ARM_EB_SMB_DOC_BASE                   0x44000000\r
#define ARM_EB_SMB_DOC_SZ                     0x04000000 /* 64 MB */\r
// SRAM\r
#define ARM_EB_SMB_SRAM_BASE                  0x48000000\r
#define ARM_EB_SMB_SRAM_SZ                    0x02000000 /* 32 MB */\r
// USB, Ethernet, VRAM\r
#define ARM_EB_SMB_PERIPH_BASE                0x4E000000\r
//#define ARM_EB_SMB_PERIPH_VRAM              0x4C000000\r
#define ARM_EB_SMB_PERIPH_SZ                  0x02000000 /* 32 MB */\r
\r
// DRAM\r
#define ARM_EB_DRAM_BASE                      0x70000000\r
#define ARM_EB_DRAM_SZ                        0x10000000\r
\r
// Logic Tile\r
#define ARM_EB_LOGIC_TILE_BASE                0xC0000000\r
#define ARM_EB_LOGIC_TILE_SZ                  0x40000000\r
\r
/*******************************************\r
// Motherboard peripherals\r
*******************************************/\r
\r
// Define MotherBoard SYS flags offsets (from ARM_EB_BOARD_PERIPH_BASE)\r
#define ARM_EB_SYS_FLAGS_REG                  (ARM_EB_BOARD_PERIPH_BASE + 0x00030)\r
#define ARM_EB_SYS_FLAGS_SET_REG              (ARM_EB_BOARD_PERIPH_BASE + 0x00030)\r
#define ARM_EB_SYS_FLAGS_CLR_REG              (ARM_EB_BOARD_PERIPH_BASE + 0x00034)\r
#define ARM_EB_SYS_FLAGS_NV_REG               (ARM_EB_BOARD_PERIPH_BASE + 0x00038)\r
#define ARM_EB_SYS_FLAGS_NV_SET_REG           (ARM_EB_BOARD_PERIPH_BASE + 0x00038)\r
#define ARM_EB_SYS_FLAGS_NV_CLR_REG           (ARM_EB_BOARD_PERIPH_BASE + 0x0003C)\r
#define ARM_EB_SYS_CLCD                       (ARM_EB_BOARD_PERIPH_BASE + 0x00050)\r
#define ARM_EB_SYS_PROCID0_REG                (ARM_EB_BOARD_PERIPH_BASE + 0x00084)\r
#define ARM_EB_SYS_PROCID1_REG                (ARM_EB_BOARD_PERIPH_BASE + 0x00088)\r
#define ARM_EB_SYS_CFGDATA_REG                (ARM_EB_BOARD_PERIPH_BASE + 0x000A0)\r
#define ARM_EB_SYS_CFGCTRL_REG                (ARM_EB_BOARD_PERIPH_BASE + 0x000A4)\r
#define ARM_EB_SYS_CFGSTAT_REG                (ARM_EB_BOARD_PERIPH_BASE + 0x000A8)\r
\r
// SP810 Controller\r
#define SP810_CTRL_BASE                       (ARM_EB_BOARD_PERIPH_BASE + 0x01000)\r
\r
// SYSTRCL Register\r
#define ARM_EB_SYSCTRL                        0x10001000\r
\r
// Uart0\r
#define PL011_CONSOLE_UART_BASE               (ARM_EB_BOARD_PERIPH_BASE + 0x09000)\r
#define PL011_CONSOLE_UART_SPEED              115200\r
\r
// SP804 Timer Bases\r
#define SP804_TIMER0_BASE                     (ARM_EB_BOARD_PERIPH_BASE + 0x11000)\r
#define SP804_TIMER1_BASE                     (ARM_EB_BOARD_PERIPH_BASE + 0x11020)\r
#define SP804_TIMER2_BASE                     (ARM_EB_BOARD_PERIPH_BASE + 0x12000)\r
#define SP804_TIMER3_BASE                     (ARM_EB_BOARD_PERIPH_BASE + 0x12020)\r
\r
// PL301 RTC\r
#define PL031_RTC_BASE                        (ARM_EB_BOARD_PERIPH_BASE + 0x17000)\r
\r
// Dynamic Memory Controller Base\r
#define ARM_EB_DMC_BASE                       0x10018000\r
\r
// Static Memory Controller Base\r
#define ARM_EB_SMC_CTRL_BASE                  0x10080000\r
\r
#define PL111_CLCD_BASE                       0x10020000\r
//TODO: FIXME ... Reserved the memory in UEFI !!! Otherwise risk of corruption\r
#define PL111_CLCD_VRAM_BASE                  0x78000000\r
\r
#define ARM_EB_SYS_OSCCLK4                    0x1000001C\r
\r
\r
/*// System Configuration Controller register Base addresses\r
//#define ARM_EB_SYS_CFG_CTRL_BASE                0x100E2000\r
#define ARM_EB_SYS_CFGRW0_REG                   0x100E2000\r
#define ARM_EB_SYS_CFGRW1_REG                   0x100E2004\r
#define ARM_EB_SYS_CFGRW2_REG                   0x100E2008\r
\r
#define ARM_EB_CFGRW1_REMAP_NOR0                0\r
#define ARM_EB_CFGRW1_REMAP_NOR1                (1 << 28)\r
#define ARM_EB_CFGRW1_REMAP_EXT_AXI             (1 << 29)\r
#define ARM_EB_CFGRW1_REMAP_DRAM                (1 << 30)\r
\r
// PL301 Fast AXI Base Address\r
#define ARM_EB_FAXI_BASE                        0x100E9000\r
\r
// L2x0 Cache Controller Base Address\r
//#define ARM_EB_L2x0_CTLR_BASE                   0x1E00A000*/\r
\r
\r
// PL031 RTC - Other settings\r
#define PL031_PPM_ACCURACY                      300000000\r
\r
/*******************************************\r
// Interrupt Map\r
*******************************************/\r
\r
// Timer Interrupts\r
#define TIMER01_INTERRUPT_NUM                34\r
#define TIMER23_INTERRUPT_NUM                35\r
\r
\r
/*******************************************\r
// EFI Memory Map in Permanent Memory (DRAM)\r
*******************************************/\r
\r
// This region is allocated at the bottom of the DRAM. It will be used\r
// for fixed address allocations such as Vector Table\r
#define ARM_EB_EFI_FIX_ADDRESS_REGION_SZ        SIZE_8MB\r
\r
// This region is the memory declared to PEI as permanent memory for PEI\r
// and DXE. EFI stacks and heaps will be declared in this region.\r
#define ARM_EB_EFI_MEMORY_REGION_SZ             0x1000000\r
#endif\r
\r
typedef enum {\r
  REVISION_XM,\r
  REVISION_UNKNOWN0,\r
  REVISION_UNKNOWN1,\r
  REVISION_UNKNOWN2,\r
  REVISION_UNKNOWN3,\r
  REVISION_C4,\r
  REVISION_C123,\r
  REVISION_AB,\r
} BEAGLEBOARD_REVISION;\r
\r
#endif\r
Commit	Line	Data
7f21c4a2	1	/** @file\r
	2	* Header defining the BeagleBoard constants (Base addresses, sizes, flags)\r
	3	*\r
	4	* Copyright (c) 2011, ARM Limited. All rights reserved.\r
7f21c4a2	5	*\r
a1594be9	6	* SPDX-License-Identifier: BSD-2-Clause-Patent\r
7f21c4a2	7	*\r
	8	**/\r
	9	\r
	10	#ifndef __BEAGLEBOARD_PLATFORM_H__\r
	11	#define __BEAGLEBOARD_PLATFORM_H__\r
	12	\r
	13	// DDR attributes\r
	14	#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r
	15	#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED\r
	16	\r
	17	// SoC registers. L3 interconnects\r
	18	#define SOC_REGISTERS_L3_PHYSICAL_BASE 0x68000000\r
	19	#define SOC_REGISTERS_L3_PHYSICAL_LENGTH 0x08000000\r
	20	#define SOC_REGISTERS_L3_ATTRIBUTES ARM_MEMORY_REGION_ATTRIBUTE_DEVICE\r
	21	\r
	22	// SoC registers. L4 interconnects\r
	23	#define SOC_REGISTERS_L4_PHYSICAL_BASE 0x48000000\r
	24	#define SOC_REGISTERS_L4_PHYSICAL_LENGTH 0x08000000\r
	25	#define SOC_REGISTERS_L4_ATTRIBUTES ARM_MEMORY_REGION_ATTRIBUTE_DEVICE\r
	26	\r
	27	\r
	28	#if 0\r
	29	/*******************************************\r
	30	// Platform Memory Map\r
	31	*******************************************/\r
	32	\r
	33	// Can be NOR, DOC, DRAM, SRAM\r
	34	#define ARM_EB_REMAP_BASE 0x00000000\r
	35	#define ARM_EB_REMAP_SZ 0x04000000\r
	36	\r
	37	// Motherboard Peripheral and On-chip peripheral\r
	38	#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE 0x10000000\r
	39	#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_SZ 0x00100000\r
	40	#define ARM_EB_BOARD_PERIPH_BASE 0x10000000\r
	41	//#define ARM_EB_CHIP_PERIPH_BASE 0x10020000\r
	42	\r
	43	// SMC\r
	44	#define ARM_EB_SMC_BASE 0x40000000\r
	45	#define ARM_EB_SMC_SZ 0x20000000\r
	46	\r
	47	// NOR Flash 1\r
	48	#define ARM_EB_SMB_NOR_BASE 0x40000000\r
	49	#define ARM_EB_SMB_NOR_SZ 0x04000000 /* 64 MB */\r
	50	// DOC Flash\r
	51	#define ARM_EB_SMB_DOC_BASE 0x44000000\r
	52	#define ARM_EB_SMB_DOC_SZ 0x04000000 /* 64 MB */\r
	53	// SRAM\r
	54	#define ARM_EB_SMB_SRAM_BASE 0x48000000\r
	55	#define ARM_EB_SMB_SRAM_SZ 0x02000000 /* 32 MB */\r
	56	// USB, Ethernet, VRAM\r
	57	#define ARM_EB_SMB_PERIPH_BASE 0x4E000000\r
	58	//#define ARM_EB_SMB_PERIPH_VRAM 0x4C000000\r
	59	#define ARM_EB_SMB_PERIPH_SZ 0x02000000 /* 32 MB */\r
	60	\r
	61	// DRAM\r
	62	#define ARM_EB_DRAM_BASE 0x70000000\r
	63	#define ARM_EB_DRAM_SZ 0x10000000\r
	64	\r
	65	// Logic Tile\r
	66	#define ARM_EB_LOGIC_TILE_BASE 0xC0000000\r
	67	#define ARM_EB_LOGIC_TILE_SZ 0x40000000\r
	68	\r
	69	/*******************************************\r
	70	// Motherboard peripherals\r
71	*******************************************/\r
72	\r
73	// Define MotherBoard SYS flags offsets (from ARM_EB_BOARD_PERIPH_BASE)\r
74	#define ARM_EB_SYS_FLAGS_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00030)\r
75	#define ARM_EB_SYS_FLAGS_SET_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00030)\r
76	#define ARM_EB_SYS_FLAGS_CLR_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00034)\r
77	#define ARM_EB_SYS_FLAGS_NV_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00038)\r
78	#define ARM_EB_SYS_FLAGS_NV_SET_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00038)\r
79	#define ARM_EB_SYS_FLAGS_NV_CLR_REG (ARM_EB_BOARD_PERIPH_BASE + 0x0003C)\r
80	#define ARM_EB_SYS_CLCD (ARM_EB_BOARD_PERIPH_BASE + 0x00050)\r
81	#define ARM_EB_SYS_PROCID0_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00084)\r
82	#define ARM_EB_SYS_PROCID1_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00088)\r
83	#define ARM_EB_SYS_CFGDATA_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A0)\r
84	#define ARM_EB_SYS_CFGCTRL_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A4)\r
85	#define ARM_EB_SYS_CFGSTAT_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A8)\r
86	\r
87	// SP810 Controller\r
88	#define SP810_CTRL_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x01000)\r
89	\r
90	// SYSTRCL Register\r
91c38d4e	91	#define ARM_EB_SYSCTRL 0x10001000\r
7f21c4a2	92	\r
	93	// Uart0\r
	94	#define PL011_CONSOLE_UART_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x09000)\r
	95	#define PL011_CONSOLE_UART_SPEED 115200\r
	96	\r
	97	// SP804 Timer Bases\r
	98	#define SP804_TIMER0_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x11000)\r
	99	#define SP804_TIMER1_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x11020)\r
	100	#define SP804_TIMER2_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x12000)\r
	101	#define SP804_TIMER3_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x12020)\r
	102	\r
	103	// PL301 RTC\r
	104	#define PL031_RTC_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x17000)\r
	105	\r
	106	// Dynamic Memory Controller Base\r
	107	#define ARM_EB_DMC_BASE 0x10018000\r
	108	\r
	109	// Static Memory Controller Base\r
	110	#define ARM_EB_SMC_CTRL_BASE 0x10080000\r
	111	\r
	112	#define PL111_CLCD_BASE 0x10020000\r
	113	//TODO: FIXME ... Reserved the memory in UEFI !!! Otherwise risk of corruption\r
	114	#define PL111_CLCD_VRAM_BASE 0x78000000\r
	115	\r
	116	#define ARM_EB_SYS_OSCCLK4 0x1000001C\r
	117	\r
	118	\r
	119	/*// System Configuration Controller register Base addresses\r
	120	//#define ARM_EB_SYS_CFG_CTRL_BASE 0x100E2000\r
	121	#define ARM_EB_SYS_CFGRW0_REG 0x100E2000\r
	122	#define ARM_EB_SYS_CFGRW1_REG 0x100E2004\r
	123	#define ARM_EB_SYS_CFGRW2_REG 0x100E2008\r
	124	\r
	125	#define ARM_EB_CFGRW1_REMAP_NOR0 0\r
	126	#define ARM_EB_CFGRW1_REMAP_NOR1 (1 << 28)\r
	127	#define ARM_EB_CFGRW1_REMAP_EXT_AXI (1 << 29)\r
	128	#define ARM_EB_CFGRW1_REMAP_DRAM (1 << 30)\r
	129	\r
	130	// PL301 Fast AXI Base Address\r
	131	#define ARM_EB_FAXI_BASE 0x100E9000\r
	132	\r
	133	// L2x0 Cache Controller Base Address\r
	134	//#define ARM_EB_L2x0_CTLR_BASE 0x1E00A000*/\r
	135	\r
	136	\r
	137	// PL031 RTC - Other settings\r
	138	#define PL031_PPM_ACCURACY 300000000\r
	139	\r
	140	/*******************************************\r
	141	// Interrupt Map\r
	142	*******************************************/\r
	143	\r
	144	// Timer Interrupts\r
	145	#define TIMER01_INTERRUPT_NUM 34\r
	146	#define TIMER23_INTERRUPT_NUM 35\r
	147	\r
	148	\r
	149	/*******************************************\r
	150	// EFI Memory Map in Permanent Memory (DRAM)\r
	151	*******************************************/\r
	152	\r
	153	// This region is allocated at the bottom of the DRAM. It will be used\r
	154	// for fixed address allocations such as Vector Table\r
	155	#define ARM_EB_EFI_FIX_ADDRESS_REGION_SZ SIZE_8MB\r
156	\r
157	// This region is the memory declared to PEI as permanent memory for PEI\r
158	// and DXE. EFI stacks and heaps will be declared in this region.\r
159	#define ARM_EB_EFI_MEMORY_REGION_SZ 0x1000000\r
160	#endif\r
161	\r
efe5f1a2	162	typedef enum {\r
	163	REVISION_XM,\r
	164	REVISION_UNKNOWN0,\r
	165	REVISION_UNKNOWN1,\r
	166	REVISION_UNKNOWN2,\r
	167	REVISION_UNKNOWN3,\r
	168	REVISION_C4,\r
	169	REVISION_C123,\r
	170	REVISION_AB,\r
	171	} BEAGLEBOARD_REVISION;\r
	172	\r
3402aac7	173	#endif\r