ArmPkg/ArmPkg.dec: Redefined PcdSystemMemory(Base|Size) as UINT64

[mirror_edk2.git] / BeagleBoardPkg / Library / BeagleBoardLib / BeagleBoardMem.c

/** @file\r
*\r
*  Copyright (c) 2011, ARM Limited. All rights reserved.\r
*  \r
*  This program and the accompanying materials                          \r
*  are licensed and made available under the terms and conditions of the BSD License         \r
*  which accompanies this distribution.  The full text of the license may be found at        \r
*  http://opensource.org/licenses/bsd-license.php                                            \r
*\r
*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
*\r
**/\r
\r
#include <Library/ArmPlatformLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/IoLib.h>\r
\r
#include <BeagleBoard.h>\r
\r
#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS          4\r
\r
/**\r
  Return the Virtual Memory Map of your platform\r
\r
  This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.\r
\r
  @param[out]   VirtualMemoryMap    Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-\r
                                    Virtual Memory mapping. This array must be ended by a zero-filled\r
                                    entry\r
\r
**/\r
VOID\r
ArmPlatformGetVirtualMemoryMap (\r
  IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap\r
  )\r
{\r
  ARM_MEMORY_REGION_ATTRIBUTES  CacheAttributes;\r
  UINTN                         Index = 0;\r
  ARM_MEMORY_REGION_DESCRIPTOR  *VirtualMemoryTable;\r
\r
  ASSERT(VirtualMemoryMap != NULL);\r
\r
  VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));\r
  if (VirtualMemoryTable == NULL) {\r
    return;\r
  }\r
\r
  if (FeaturePcdGet(PcdCacheEnable) == TRUE) {\r
    CacheAttributes = DDR_ATTRIBUTES_CACHED;\r
  } else {\r
    CacheAttributes = DDR_ATTRIBUTES_UNCACHED;\r
  }\r
\r
  // ReMap (Either NOR Flash or DRAM)\r
  VirtualMemoryTable[Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);\r
  VirtualMemoryTable[Index].VirtualBase  = PcdGet64 (PcdSystemMemoryBase);\r
  VirtualMemoryTable[Index].Length       = PcdGet64 (PcdSystemMemorySize);\r
  VirtualMemoryTable[Index].Attributes   = CacheAttributes;\r
\r
  // SOC Registers. L3 interconnects\r
  VirtualMemoryTable[++Index].PhysicalBase = SOC_REGISTERS_L3_PHYSICAL_BASE;\r
  VirtualMemoryTable[Index].VirtualBase  = SOC_REGISTERS_L3_PHYSICAL_BASE;\r
  VirtualMemoryTable[Index].Length       = SOC_REGISTERS_L3_PHYSICAL_LENGTH;\r
  VirtualMemoryTable[Index].Attributes   = SOC_REGISTERS_L3_ATTRIBUTES;\r
\r
  // SOC Registers. L4 interconnects\r
  VirtualMemoryTable[++Index].PhysicalBase = SOC_REGISTERS_L4_PHYSICAL_BASE;\r
  VirtualMemoryTable[Index].VirtualBase  = SOC_REGISTERS_L4_PHYSICAL_BASE;\r
  VirtualMemoryTable[Index].Length       = SOC_REGISTERS_L4_PHYSICAL_LENGTH;\r
  VirtualMemoryTable[Index].Attributes   = SOC_REGISTERS_L4_ATTRIBUTES;\r
\r
  // End of Table\r
  VirtualMemoryTable[++Index].PhysicalBase = 0;\r
  VirtualMemoryTable[Index].VirtualBase  = 0;\r
  VirtualMemoryTable[Index].Length       = 0;\r
  VirtualMemoryTable[Index].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
\r
  ASSERT((Index + 1) == MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);\r
\r
  *VirtualMemoryMap = VirtualMemoryTable;\r
}\r