projects / mirror_edk2.git / blame
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|---|---|---|
| 2ef2b01e A |
1 | /** @file\r |
| 2 | \r | |
| 3 | Copyright (c) 2008-2009, Apple Inc. All rights reserved.\r | |
| 4 | \r | |
| 5 | All rights reserved. This program and the accompanying materials\r | |
| 6 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 7 | which accompanies this distribution. The full text of the license may be found at\r | |
| 8 | http://opensource.org/licenses/bsd-license.php\r | |
| 9 | \r | |
| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 12 | \r | |
| 13 | **/\r | |
| 14 | \r | |
| 15 | #include <Library/IoLib.h>\r | |
| 16 | #include <Library/DebugLib.h>\r | |
| 17 | \r | |
| 18 | #include <Omap3530/Omap3530.h>\r | |
| 19 | \r | |
| 20 | VOID\r | |
| 21 | ClockInit (\r | |
| 22 | VOID\r | |
| 23 | )\r | |
| 24 | {\r | |
| 25 | //DPLL1 - DPLL4 are configured part of Configuration header which OMAP3 ROM parses.\r | |
| 26 | \r | |
| 27 | // Enable PLL5 and set to 120 MHz as a reference clock.\r | |
| 28 | MmioWrite32(CM_CLKSEL4_PLL, CM_CLKSEL_PLL_MULT(120) | CM_CLKSEL_PLL_DIV(13));\r | |
| 29 | MmioWrite32(CM_CLKSEL5_PLL, CM_CLKSEL_DIV_120M(1));\r | |
| 30 | MmioWrite32(CM_CLKEN2_PLL, CM_CLKEN_FREQSEL_075_100 | CM_CLKEN_ENABLE);\r | |
| 31 | \r | |
| 32 | // Turn on functional & interface clocks to the USBHOST power domain\r | |
| 33 | MmioOr32(CM_FCLKEN_USBHOST, CM_FCLKEN_USBHOST_EN_USBHOST2_ENABLE\r | |
| 34 | | CM_FCLKEN_USBHOST_EN_USBHOST1_ENABLE);\r | |
| 35 | MmioOr32(CM_ICLKEN_USBHOST, CM_ICLKEN_USBHOST_EN_USBHOST_ENABLE);\r | |
| 36 | \r | |
| 37 | // Turn on functional & interface clocks to the USBTLL block.\r | |
| 38 | MmioOr32(CM_FCLKEN3_CORE, CM_FCLKEN3_CORE_EN_USBTLL_ENABLE);\r | |
| 39 | MmioOr32(CM_ICLKEN3_CORE, CM_ICLKEN3_CORE_EN_USBTLL_ENABLE);\r | |
| 40 | \r | |
| 41 | // Turn on functional & interface clocks to MMC1 and I2C1 modules.\r | |
| 42 | MmioOr32(CM_FCLKEN1_CORE, CM_FCLKEN1_CORE_EN_MMC1_ENABLE\r | |
| 43 | | CM_FCLKEN1_CORE_EN_I2C1_ENABLE);\r | |
| 44 | MmioOr32(CM_ICLKEN1_CORE, CM_ICLKEN1_CORE_EN_MMC1_ENABLE\r | |
| 45 | | CM_ICLKEN1_CORE_EN_I2C1_ENABLE);\r | |
| 46 | \r | |
| 47 | // Turn on functional & interface clocks to various Peripherals.\r | |
| 48 | MmioOr32(CM_FCLKEN_PER, CM_FCLKEN_PER_EN_UART3_ENABLE\r | |
| 49 | | CM_FCLKEN_PER_EN_GPT3_ENABLE\r | |
| 50 | | CM_FCLKEN_PER_EN_GPT4_ENABLE\r | |
| 51 | | CM_FCLKEN_PER_EN_GPIO2_ENABLE\r | |
| 52 | | CM_FCLKEN_PER_EN_GPIO3_ENABLE\r | |
| 53 | | CM_FCLKEN_PER_EN_GPIO4_ENABLE\r | |
| 54 | | CM_FCLKEN_PER_EN_GPIO5_ENABLE\r | |
| 55 | | CM_FCLKEN_PER_EN_GPIO6_ENABLE);\r | |
| 56 | MmioOr32(CM_ICLKEN_PER, CM_ICLKEN_PER_EN_UART3_ENABLE\r | |
| 57 | | CM_ICLKEN_PER_EN_GPT3_ENABLE\r | |
| 58 | | CM_ICLKEN_PER_EN_GPT4_ENABLE\r | |
| 59 | | CM_ICLKEN_PER_EN_GPIO2_ENABLE\r | |
| 60 | | CM_ICLKEN_PER_EN_GPIO3_ENABLE\r | |
| 61 | | CM_ICLKEN_PER_EN_GPIO4_ENABLE\r | |
| 62 | | CM_ICLKEN_PER_EN_GPIO5_ENABLE\r | |
| 63 | | CM_ICLKEN_PER_EN_GPIO6_ENABLE);\r | |
| 64 | \r | |
| 65 | // Turn on functional & inteface clocks to various wakeup modules.\r | |
| 66 | MmioOr32(CM_FCLKEN_WKUP, CM_FCLKEN_WKUP_EN_GPIO1_ENABLE\r | |
| 67 | | CM_FCLKEN_WKUP_EN_WDT2_ENABLE);\r | |
| 68 | MmioOr32(CM_ICLKEN_WKUP, CM_ICLKEN_WKUP_EN_GPIO1_ENABLE\r | |
| 69 | | CM_ICLKEN_WKUP_EN_WDT2_ENABLE);\r | |
| 70 | }\r |