Fix the build break in two open source packages caused by check in 10660.
[mirror_edk2.git] / BeagleBoardPkg / Sec / Sec.c
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1/** @file\r
2 C Entry point for the SEC. First C code after the reset vector.\r
3\r
1ebd6c11 4 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
2ef2b01e 5 \r
1ebd6c11 6 This program and the accompanying materials\r
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7 are licensed and made available under the terms and conditions of the BSD License\r
8 which accompanies this distribution. The full text of the license may be found at\r
9 http://opensource.org/licenses/bsd-license.php\r
10\r
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14**/\r
15\r
16#include <PiPei.h>\r
17\r
18#include <Library/DebugLib.h>\r
19#include <Library/PrePiLib.h>\r
20#include <Library/PcdLib.h>\r
21#include <Library/IoLib.h>\r
22#include <Library/OmapLib.h>\r
23#include <Library/ArmLib.h>\r
225290eb 24#include <Library/PeCoffGetEntryPointLib.h>\r
5b792f1a 25#include <Library/DebugAgentLib.h>\r
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26\r
27#include <Ppi/GuidedSectionExtraction.h>\r
ca3ad58b 28#include <Guid/LzmaDecompress.h>\r
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29#include <Omap3530/Omap3530.h>\r
30\r
ca3ad58b 31#include "LzmaDecompress.h"\r
32\r
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33VOID\r
34PadConfiguration (\r
35 VOID\r
36 );\r
37\r
38VOID\r
39ClockInit (\r
40 VOID\r
41 );\r
42\r
5b792f1a 43\r
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44VOID\r
45TimerInit (\r
46 VOID\r
47 )\r
48{\r
7e353851 49 UINTN Timer = FixedPcdGet32(PcdOmap35xxFreeTimer);\r
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50 UINT32 TimerBaseAddress = TimerBase(Timer);\r
51\r
52 // Set source clock for GPT3 & GPT4 to SYS_CLK\r
5b792f1a 53 MmioOr32 (CM_CLKSEL_PER, CM_CLKSEL_PER_CLKSEL_GPT3_SYS | CM_CLKSEL_PER_CLKSEL_GPT4_SYS);\r
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54\r
55 // Set count & reload registers\r
026e30c4 56 MmioWrite32 (TimerBaseAddress + GPTIMER_TCRR, 0x00000000);\r
57 MmioWrite32 (TimerBaseAddress + GPTIMER_TLDR, 0x00000000);\r
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58\r
59 // Disable interrupts\r
026e30c4 60 MmioWrite32 (TimerBaseAddress + GPTIMER_TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_DISABLE | TIER_MAT_IT_DISABLE);\r
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61\r
62 // Start Timer\r
026e30c4 63 MmioWrite32 (TimerBaseAddress + GPTIMER_TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);\r
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64\r
65 //Disable OMAP Watchdog timer (WDT2)\r
026e30c4 66 MmioWrite32 (WDTIMER2_BASE + WSPR, 0xAAAA);\r
2ef2b01e 67 DEBUG ((EFI_D_ERROR, "Magic delay to disable watchdog timers properly.\n"));\r
026e30c4 68 MmioWrite32 (WDTIMER2_BASE + WSPR, 0x5555);\r
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69}\r
70\r
71VOID\r
72UartInit (\r
73 VOID\r
74 )\r
75{\r
7e353851 76 UINTN Uart = FixedPcdGet32(PcdOmap35xxConsoleUart);\r
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77 UINT32 UartBaseAddress = UartBase(Uart);\r
78\r
79 // Set MODE_SELECT=DISABLE before trying to initialize or modify DLL, DLH registers.\r
026e30c4 80 MmioWrite32 (UartBaseAddress + UART_MDR1_REG, UART_MDR1_MODE_SELECT_DISABLE);\r
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81\r
82 // Put device in configuration mode.\r
026e30c4 83 MmioWrite32 (UartBaseAddress + UART_LCR_REG, UART_LCR_DIV_EN_ENABLE);\r
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84\r
85 // Programmable divisor N = 48Mhz/16/115200 = 26\r
026e30c4 86 MmioWrite32 (UartBaseAddress + UART_DLL_REG, 3000000/FixedPcdGet64 (PcdUartDefaultBaudRate)); // low divisor\r
87 MmioWrite32 (UartBaseAddress + UART_DLH_REG, 0); // high divisor\r
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88\r
89 // Enter into UART operational mode.\r
026e30c4 90 MmioWrite32 (UartBaseAddress + UART_LCR_REG, UART_LCR_DIV_EN_DISABLE | UART_LCR_CHAR_LENGTH_8);\r
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91\r
92 // Force DTR and RTS output to active\r
026e30c4 93 MmioWrite32 (UartBaseAddress + UART_MCR_REG, UART_MCR_RTS_FORCE_ACTIVE | UART_MCR_DTR_FORCE_ACTIVE);\r
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94\r
95 // Clear & enable fifos\r
026e30c4 96 MmioWrite32 (UartBaseAddress + UART_FCR_REG, UART_FCR_TX_FIFO_CLEAR | UART_FCR_RX_FIFO_CLEAR | UART_FCR_FIFO_ENABLE); \r
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97\r
98 // Restore MODE_SELECT \r
026e30c4 99 MmioWrite32 (UartBaseAddress + UART_MDR1_REG, UART_MDR1_MODE_SELECT_UART_16X);\r
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100}\r
101\r
102VOID\r
103InitCache (\r
104 IN UINT32 MemoryBase,\r
105 IN UINT32 MemoryLength\r
106 );\r
107\r
108EFI_STATUS\r
109EFIAPI\r
110ExtractGuidedSectionLibConstructor (\r
111 VOID\r
112 );\r
113\r
114EFI_STATUS\r
115EFIAPI\r
116LzmaDecompressLibConstructor (\r
117 VOID\r
118 );\r
119\r
225290eb 120\r
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121VOID\r
122CEntryPoint (\r
123 IN VOID *MemoryBase,\r
124 IN UINTN MemorySize,\r
125 IN VOID *StackBase,\r
126 IN UINTN StackSize\r
127 )\r
128{\r
129 VOID *HobBase;\r
130\r
14e00c13 131 // Build a basic HOB list\r
132 HobBase = (VOID *)(UINTN)(FixedPcdGet32(PcdEmbeddedFdBaseAddress) + FixedPcdGet32(PcdEmbeddedFdSize));\r
133 CreateHobList (MemoryBase, MemorySize, HobBase, StackBase);\r
134\r
2ef2b01e 135 //Set up Pin muxing.\r
026e30c4 136 PadConfiguration ();\r
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137\r
138 // Set up system clocking\r
026e30c4 139 ClockInit ();\r
2ef2b01e 140\r
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141\r
142 // Enable program flow prediction, if supported.\r
026e30c4 143 ArmEnableBranchPrediction ();\r
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144\r
145 // Initialize CPU cache\r
026e30c4 146 InitCache ((UINT32)MemoryBase, (UINT32)MemorySize);\r
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147\r
148 // Add memory allocation hob for relocated FD\r
026e30c4 149 BuildMemoryAllocationHob (FixedPcdGet32(PcdEmbeddedFdBaseAddress), FixedPcdGet32(PcdEmbeddedFdSize), EfiBootServicesData);\r
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150\r
151 // Add the FVs to the hob list\r
026e30c4 152 BuildFvHob (PcdGet32(PcdFlashFvMainBase), PcdGet32(PcdFlashFvMainSize));\r
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153\r
154 // Start talking\r
026e30c4 155 UartInit ();\r
5b792f1a 156 \r
7c137cae 157 InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL);\r
5b792f1a 158 SaveAndSetDebugTimerInterrupt (TRUE);\r
225290eb 159\r
5b792f1a 160 DEBUG ((EFI_D_ERROR, "UART Enabled\n"));\r
2ef2b01e 161\r
b830c1df 162 // Start up a free running timer so that the timer lib will work\r
026e30c4 163 TimerInit ();\r
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164\r
165 // SEC phase needs to run library constructors by hand.\r
026e30c4 166 ExtractGuidedSectionLibConstructor ();\r
167 LzmaDecompressLibConstructor ();\r
2ef2b01e 168\r
ca3ad58b 169 // Build HOBs to pass up our version of stuff the DXE Core needs to save space\r
ca3ad58b 170 BuildPeCoffLoaderHob ();\r
171 BuildExtractSectionHob (\r
172 &gLzmaCustomDecompressGuid,\r
173 LzmaGuidedSectionGetInfo,\r
174 LzmaGuidedSectionExtraction\r
175 );\r
ca3ad58b 176\r
14e00c13 177 // Assume the FV that contains the SEC (our code) also contains a compressed FV.\r
8c3f387b 178 DecompressFirstFv ();\r
179\r
2ef2b01e 180 // Load the DXE Core and transfer control to it\r
026e30c4 181 LoadDxeCoreFromFv (NULL, 0);\r
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182 \r
183 // DXE Core should always load and never return\r
026e30c4 184 ASSERT (FALSE);\r
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185}\r
186\r