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1 | /** @file\r |
2 | C Entry point for the SEC. First C code after the reset vector.\r | |
3 | \r | |
4 | Copyright (c) 2008-2009, Apple Inc. All rights reserved.\r | |
5 | \r | |
6 | All rights reserved. This program and the accompanying materials\r | |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #include <PiPei.h>\r | |
17 | \r | |
18 | #include <Library/DebugLib.h>\r | |
19 | #include <Library/PrePiLib.h>\r | |
20 | #include <Library/PcdLib.h>\r | |
21 | #include <Library/IoLib.h>\r | |
22 | #include <Library/OmapLib.h>\r | |
23 | #include <Library/ArmLib.h>\r | |
24 | \r | |
25 | #include <Ppi/GuidedSectionExtraction.h>\r | |
26 | \r | |
27 | #include <Omap3530/Omap3530.h>\r | |
28 | \r | |
29 | VOID\r | |
30 | PadConfiguration (\r | |
31 | VOID\r | |
32 | );\r | |
33 | \r | |
34 | VOID\r | |
35 | ClockInit (\r | |
36 | VOID\r | |
37 | );\r | |
38 | \r | |
39 | VOID\r | |
40 | TimerInit (\r | |
41 | VOID\r | |
42 | )\r | |
43 | {\r | |
44 | UINTN Timer = FixedPcdGet32(PcdBeagleFreeTimer);\r | |
45 | UINT32 TimerBaseAddress = TimerBase(Timer);\r | |
46 | \r | |
47 | // Set source clock for GPT3 & GPT4 to SYS_CLK\r | |
48 | MmioOr32(CM_CLKSEL_PER, CM_CLKSEL_PER_CLKSEL_GPT3_SYS \r | |
49 | | CM_CLKSEL_PER_CLKSEL_GPT4_SYS);\r | |
50 | \r | |
51 | // Set count & reload registers\r | |
52 | MmioWrite32(TimerBaseAddress + GPTIMER_TCRR, 0x00000000);\r | |
53 | MmioWrite32(TimerBaseAddress + GPTIMER_TLDR, 0x00000000);\r | |
54 | \r | |
55 | // Disable interrupts\r | |
56 | MmioWrite32(TimerBaseAddress + GPTIMER_TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_DISABLE | TIER_MAT_IT_DISABLE);\r | |
57 | \r | |
58 | // Start Timer\r | |
59 | MmioWrite32(TimerBaseAddress + GPTIMER_TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);\r | |
60 | \r | |
61 | //Disable OMAP Watchdog timer (WDT2)\r | |
62 | MmioWrite32(WDTIMER2_BASE + WSPR, 0xAAAA);\r | |
63 | DEBUG ((EFI_D_ERROR, "Magic delay to disable watchdog timers properly.\n"));\r | |
64 | MmioWrite32(WDTIMER2_BASE + WSPR, 0x5555);\r | |
65 | }\r | |
66 | \r | |
67 | VOID\r | |
68 | UartInit (\r | |
69 | VOID\r | |
70 | )\r | |
71 | {\r | |
72 | UINTN Uart = FixedPcdGet32(PcdBeagleConsoleUart);\r | |
73 | UINT32 UartBaseAddress = UartBase(Uart);\r | |
74 | \r | |
75 | // Set MODE_SELECT=DISABLE before trying to initialize or modify DLL, DLH registers.\r | |
76 | MmioWrite32(UartBaseAddress + UART_MDR1_REG, UART_MDR1_MODE_SELECT_DISABLE);\r | |
77 | \r | |
78 | // Put device in configuration mode.\r | |
79 | MmioWrite32(UartBaseAddress + UART_LCR_REG, UART_LCR_DIV_EN_ENABLE);\r | |
80 | \r | |
81 | // Programmable divisor N = 48Mhz/16/115200 = 26\r | |
82 | MmioWrite32(UartBaseAddress + UART_DLL_REG, 26); // low divisor\r | |
83 | MmioWrite32(UartBaseAddress + UART_DLH_REG, 0); // high divisor\r | |
84 | \r | |
85 | // Enter into UART operational mode.\r | |
86 | MmioWrite32(UartBaseAddress + UART_LCR_REG, UART_LCR_DIV_EN_DISABLE | UART_LCR_CHAR_LENGTH_8);\r | |
87 | \r | |
88 | // Force DTR and RTS output to active\r | |
89 | MmioWrite32(UartBaseAddress + UART_MCR_REG, UART_MCR_RTS_FORCE_ACTIVE | UART_MCR_DTR_FORCE_ACTIVE);\r | |
90 | \r | |
91 | // Clear & enable fifos\r | |
92 | MmioWrite32(UartBaseAddress + UART_FCR_REG, UART_FCR_TX_FIFO_CLEAR | UART_FCR_RX_FIFO_CLEAR | UART_FCR_FIFO_ENABLE); \r | |
93 | \r | |
94 | // Restore MODE_SELECT \r | |
95 | MmioWrite32(UartBaseAddress + UART_MDR1_REG, UART_MDR1_MODE_SELECT_UART_16X);\r | |
96 | }\r | |
97 | \r | |
98 | VOID\r | |
99 | InitCache (\r | |
100 | IN UINT32 MemoryBase,\r | |
101 | IN UINT32 MemoryLength\r | |
102 | );\r | |
103 | \r | |
104 | EFI_STATUS\r | |
105 | EFIAPI\r | |
106 | ExtractGuidedSectionLibConstructor (\r | |
107 | VOID\r | |
108 | );\r | |
109 | \r | |
110 | EFI_STATUS\r | |
111 | EFIAPI\r | |
112 | LzmaDecompressLibConstructor (\r | |
113 | VOID\r | |
114 | );\r | |
115 | \r | |
116 | VOID\r | |
117 | CEntryPoint (\r | |
118 | IN VOID *MemoryBase,\r | |
119 | IN UINTN MemorySize,\r | |
120 | IN VOID *StackBase,\r | |
121 | IN UINTN StackSize\r | |
122 | )\r | |
123 | {\r | |
124 | VOID *HobBase;\r | |
125 | \r | |
126 | //Set up Pin muxing.\r | |
127 | PadConfiguration();\r | |
128 | \r | |
129 | // Set up system clocking\r | |
130 | ClockInit();\r | |
131 | \r | |
132 | // Build a basic HOB list\r | |
133 | HobBase = (VOID *)(UINTN)(FixedPcdGet32(PcdEmbeddedFdBaseAddress) + FixedPcdGet32(PcdEmbeddedFdSize));\r | |
134 | CreateHobList(MemoryBase, MemorySize, HobBase, StackBase);\r | |
135 | \r | |
136 | // Enable program flow prediction, if supported.\r | |
137 | ArmEnableBranchPrediction();\r | |
138 | \r | |
139 | // Initialize CPU cache\r | |
140 | InitCache((UINT32)MemoryBase, (UINT32)MemorySize);\r | |
141 | \r | |
142 | // Add memory allocation hob for relocated FD\r | |
143 | BuildMemoryAllocationHob(FixedPcdGet32(PcdEmbeddedFdBaseAddress), FixedPcdGet32(PcdEmbeddedFdSize), EfiBootServicesData);\r | |
144 | \r | |
145 | // Add the FVs to the hob list\r | |
146 | BuildFvHob(PcdGet32(PcdFlashFvMainBase), PcdGet32(PcdFlashFvMainSize));\r | |
147 | \r | |
148 | // Start talking\r | |
149 | UartInit();\r | |
150 | DEBUG((EFI_D_ERROR, "UART Test Line\n"));\r | |
151 | \r | |
152 | // Start up a free running time so that the timer lib will work\r | |
153 | TimerInit();\r | |
154 | \r | |
155 | // SEC phase needs to run library constructors by hand.\r | |
156 | ExtractGuidedSectionLibConstructor();\r | |
157 | LzmaDecompressLibConstructor();\r | |
158 | \r | |
159 | // Load the DXE Core and transfer control to it\r | |
160 | LoadDxeCoreFromFv(NULL, 0);\r | |
161 | \r | |
162 | // DXE Core should always load and never return\r | |
163 | ASSERT(FALSE);\r | |
164 | }\r | |
165 | \r |