]> git.proxmox.com Git - mirror_edk2.git/blame - CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
projects / mirror_edk2.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
CorebootModulePkg/PciHostBridgeLib: Fix PCI 64bit memory BAR size issue
[mirror_edk2.git] / CorebootPayloadPkg / Library / PciHostBridgeLib / PciHostBridgeSupport.c
CommitLineData
69787a9d
MM		 1/** @file\r
2 Scan the entire PCI bus for root bridges to support coreboot UEFI payload.\r
3\r
4 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
5\r
6 This program and the accompanying materials are licensed and made available\r
7 under the terms and conditions of the BSD License which accompanies this\r
8 distribution. The full text of the license may be found at\r
9 http://opensource.org/licenses/bsd-license.php.\r
10\r
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
12 WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14**/\r
15\r
16#include <PiDxe.h>\r
17#include <IndustryStandard/Pci.h>\r
18#include <Protocol/PciHostBridgeResourceAllocation.h>\r
19#include <Protocol/PciRootBridgeIo.h>\r
20#include <Library/BaseMemoryLib.h>\r
21#include <Library/DebugLib.h>\r
22#include <Library/MemoryAllocationLib.h>\r
23#include <Library/PciHostBridgeLib.h>\r
24#include <Library/PciLib.h>\r
25#include "PciHostBridge.h"\r
26\r
27/**\r
28 Adjust the collected PCI resource.\r
29\r
30 @param[in] Io IO aperture.\r
31\r
32 @param[in] Mem MMIO aperture.\r
33\r
34 @param[in] MemAbove4G MMIO aperture above 4G.\r
35\r
36 @param[in] PMem Prefetchable MMIO aperture.\r
37\r
38 @param[in] PMemAbove4G Prefetchable MMIO aperture above 4G.\r
39**/\r
40VOID\r
41AdjustRootBridgeResource (\r
42 IN PCI_ROOT_BRIDGE_APERTURE *Io,\r
43 IN PCI_ROOT_BRIDGE_APERTURE *Mem,\r
44 IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,\r
45 IN PCI_ROOT_BRIDGE_APERTURE *PMem,\r
46 IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G\r
47)\r
48{\r
49 UINT64 Mask;\r
50\r
51 //\r
52 // For now try to downgrade everything into MEM32 since\r
53 // - coreboot does not assign resource above 4GB\r
54 // - coreboot might allocate interleaved MEM32 and PMEM32 resource\r
55 // in some cases\r
56 //\r
57 if (PMem->Base < Mem->Base) {\r
58 Mem->Base = PMem->Base;\r
59 }\r
60\r
61 if (PMem->Limit > Mem->Limit) {\r
62 Mem->Limit = PMem->Limit;\r
63 }\r
64\r
65 PMem->Base = MAX_UINT64;\r
66 PMem->Limit = 0;\r
67\r
68 if (MemAbove4G->Base < 0x100000000ULL) {\r
69 if (MemAbove4G->Base < Mem->Base) {\r
70 Mem->Base = MemAbove4G->Base;\r
71 }\r
72 if (MemAbove4G->Limit > Mem->Limit) {\r
73 Mem->Limit = MemAbove4G->Limit;\r
74 }\r
75 MemAbove4G->Base = MAX_UINT64;\r
76 MemAbove4G->Limit = 0;\r
77 }\r
78\r
79 if (PMemAbove4G->Base < 0x100000000ULL) {\r
80 if (PMemAbove4G->Base < Mem->Base) {\r
81 Mem->Base = PMemAbove4G->Base;\r
82 }\r
83 if (PMemAbove4G->Limit > Mem->Limit) {\r
84 Mem->Limit = PMemAbove4G->Limit;\r
85 }\r
86 PMemAbove4G->Base = MAX_UINT64;\r
87 PMemAbove4G->Limit = 0;\r
88 }\r
89\r
90 //\r
91 // Align IO resource at 4K boundary\r
92 //\r
93 Mask = 0xFFFULL;\r
94 Io->Limit = (Io->Limit + Mask) & ~Mask;\r
95 if (Io->Base != MAX_UINT64) {\r
96 Io->Base &= ~Mask;\r
97 }\r
98\r
99 //\r
100 // Align MEM resource at 1MB boundary\r
101 //\r
102 Mask = 0xFFFFFULL;\r
103 Mem->Limit = (Mem->Limit + Mask) & ~Mask;\r
104 if (Mem->Base != MAX_UINT64) {\r
105 Mem->Base &= ~Mask;\r
106 }\r
107}\r
108\r
109/**\r
110 Probe a bar is existed or not.\r
111\r
112 @param[in] Address PCI address for the BAR.\r
113 @param[out] OriginalValue The original bar value returned.\r
114 @param[out] Value The probed bar value returned.\r
115**/\r
116STATIC\r
117VOID\r
118PcatPciRootBridgeBarExisted (\r
119 IN UINT64 Address,\r
120 OUT UINT32 *OriginalValue,\r
121 OUT UINT32 *Value\r
122)\r
123{\r
124 UINTN PciAddress;\r
125\r
126 PciAddress = (UINTN)Address;\r
127\r
128 //\r
129 // Preserve the original value\r
130 //\r
131 *OriginalValue = PciRead32 (PciAddress);\r
132\r
133 //\r
134 // Disable timer interrupt while the BAR is probed\r
135 //\r
136 DisableInterrupts ();\r
137\r
138 PciWrite32 (PciAddress, 0xFFFFFFFF);\r
139 *Value = PciRead32 (PciAddress);\r
140 PciWrite32 (PciAddress, *OriginalValue);\r
141\r
142 //\r
143 // Enable interrupt\r
144 //\r
145 EnableInterrupts ();\r
146}\r
147\r
148/**\r
149 Parse PCI bar and collect the assigned PCI resouce information.\r
150\r
151 @param[in] Command Supported attributes.\r
152\r
153 @param[in] Bus PCI bus number.\r
154\r
155 @param[in] Device PCI device number.\r
156\r
157 @param[in] Function PCI function number.\r
158\r
159 @param[in] BarOffsetBase PCI bar start offset.\r
160\r
161 @param[in] BarOffsetEnd PCI bar end offset.\r
162\r
163 @param[in] Io IO aperture.\r
164\r
165 @param[in] Mem MMIO aperture.\r
166\r
167 @param[in] MemAbove4G MMIO aperture above 4G.\r
168\r
169 @param[in] PMem Prefetchable MMIO aperture.\r
170\r
171 @param[in] PMemAbove4G Prefetchable MMIO aperture above 4G.\r
172**/\r
173STATIC\r
174VOID\r
175PcatPciRootBridgeParseBars (\r
176 IN UINT16 Command,\r
177 IN UINTN Bus,\r
178 IN UINTN Device,\r
179 IN UINTN Function,\r
180 IN UINTN BarOffsetBase,\r
181 IN UINTN BarOffsetEnd,\r
182 IN PCI_ROOT_BRIDGE_APERTURE *Io,\r
183 IN PCI_ROOT_BRIDGE_APERTURE *Mem,\r
184 IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,\r
185 IN PCI_ROOT_BRIDGE_APERTURE *PMem,\r
186 IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G\r
187\r
188)\r
189{\r
190 UINT32 OriginalValue;\r
191 UINT32 Value;\r
192 UINT32 OriginalUpperValue;\r
193 UINT32 UpperValue;\r
194 UINT64 Mask;\r
195 UINTN Offset;\r
8a3a9781 196 UINTN LowBit;\r
69787a9d
MM		 197 UINT64 Base;\r
198 UINT64 Length;\r
199 UINT64 Limit;\r
200 PCI_ROOT_BRIDGE_APERTURE *MemAperture;\r
201\r
202 for (Offset = BarOffsetBase; Offset < BarOffsetEnd; Offset += sizeof (UINT32)) {\r
203 PcatPciRootBridgeBarExisted (\r
204 PCI_LIB_ADDRESS (Bus, Device, Function, Offset),\r
205 &OriginalValue, &Value\r
206 );\r
207 if (Value == 0) {\r
208 continue;\r
209 }\r
210 if ((Value & BIT0) == BIT0) {\r
211 //\r
212 // IO Bar\r
213 //\r
214 if (Command & EFI_PCI_COMMAND_IO_SPACE) {\r
215 Mask = 0xfffffffc;\r
216 Base = OriginalValue & Mask;\r
217 Length = ((~(Value & Mask)) & Mask) + 0x04;\r
218 if (!(Value & 0xFFFF0000)) {\r
219 Length &= 0x0000FFFF;\r
220 }\r
221 Limit = Base + Length - 1;\r
222\r
223 if ((Base > 0) && (Base < Limit)) {\r
224 if (Io->Base > Base) {\r
225 Io->Base = Base;\r
226 }\r
227 if (Io->Limit < Limit) {\r
228 Io->Limit = Limit;\r
229 }\r
230 }\r
231 }\r
232 } else {\r
233 //\r
234 // Mem Bar\r
235 //\r
236 if (Command & EFI_PCI_COMMAND_MEMORY_SPACE) {\r
237\r
238 Mask = 0xfffffff0;\r
239 Base = OriginalValue & Mask;\r
240 Length = Value & Mask;\r
241\r
242 if ((Value & (BIT1 | BIT2)) == 0) {\r
243 //\r
244 // 32bit\r
245 //\r
246 Length = ((~Length) + 1) & 0xffffffff;\r
247\r
248 if ((Value & BIT3) == BIT3) {\r
249 MemAperture = PMem;\r
250 } else {\r
251 MemAperture = Mem;\r
252 }\r
253 } else {\r
254 //\r
255 // 64bit\r
256 //\r
257 Offset += 4;\r
258 PcatPciRootBridgeBarExisted (\r
259 PCI_LIB_ADDRESS (Bus, Device, Function, Offset),\r
260 &OriginalUpperValue,\r
261 &UpperValue\r
262 );\r
263\r
264 Base = Base | LShiftU64 ((UINT64) OriginalUpperValue, 32);\r
265 Length = Length | LShiftU64 ((UINT64) UpperValue, 32);\r
8a3a9781
MM		 266 if (Length != 0) {\r
267 LowBit = LowBitSet64 (Length);\r
268 Length = LShiftU64 (1ULL, LowBit);\r
269 }\r
69787a9d
MM		 270\r
271 if ((Value & BIT3) == BIT3) {\r
272 MemAperture = PMemAbove4G;\r
273 } else {\r
274 MemAperture = MemAbove4G;\r
275 }\r
276 }\r
277\r
278 Limit = Base + Length - 1;\r
279 if ((Base > 0) && (Base < Limit)) {\r
280 if (MemAperture->Base > Base) {\r
281 MemAperture->Base = Base;\r
282 }\r
283 if (MemAperture->Limit < Limit) {\r
284 MemAperture->Limit = Limit;\r
285 }\r
286 }\r
287 }\r
288 }\r
289 }\r
290}\r
291\r
292/**\r
293 Scan for all root bridges in platform.\r
294\r
295 @param[out] NumberOfRootBridges Number of root bridges detected\r
296\r
297 @retval Pointer to the allocated PCI_ROOT_BRIDGE structure array.\r
298**/\r
299PCI_ROOT_BRIDGE *\r
300ScanForRootBridges (\r
301 OUT UINTN *NumberOfRootBridges\r
302)\r
303{\r
304 UINTN PrimaryBus;\r
305 UINTN SubBus;\r
306 UINT8 Device;\r
307 UINT8 Function;\r
308 UINTN NumberOfDevices;\r
309 UINTN Address;\r
310 PCI_TYPE01 Pci;\r
311 UINT64 Attributes;\r
312 UINT64 Base;\r
313 UINT64 Limit;\r
314 UINT64 Value;\r
315 PCI_ROOT_BRIDGE_APERTURE Io, Mem, MemAbove4G, PMem, PMemAbove4G, *MemAperture;\r
316 PCI_ROOT_BRIDGE *RootBridges;\r
317 UINTN BarOffsetEnd;\r
318\r
319\r
320 *NumberOfRootBridges = 0;\r
321 RootBridges = NULL;\r
322\r
323 //\r
324 // After scanning all the PCI devices on the PCI root bridge's primary bus,\r
325 // update the Primary Bus Number for the next PCI root bridge to be this PCI\r
326 // root bridge's subordinate bus number + 1.\r
327 //\r
328 for (PrimaryBus = 0; PrimaryBus <= PCI_MAX_BUS; PrimaryBus = SubBus + 1) {\r
329 SubBus = PrimaryBus;\r
330 Attributes = 0;\r
331 Io.Base = Mem.Base = MemAbove4G.Base = PMem.Base = PMemAbove4G.Base = MAX_UINT64;\r
332 Io.Limit = Mem.Limit = MemAbove4G.Limit = PMem.Limit = PMemAbove4G.Limit = 0;\r
333 //\r
334 // Scan all the PCI devices on the primary bus of the PCI root bridge\r
335 //\r
336 for (Device = 0, NumberOfDevices = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
337\r
338 for (Function = 0; Function <= PCI_MAX_FUNC; Function++) {\r
339\r
340 //\r
341 // Compute the PCI configuration address of the PCI device to probe\r
342 //\r
343 Address = PCI_LIB_ADDRESS (PrimaryBus, Device, Function, 0);\r
344\r
345 //\r
346 // Read the Vendor ID from the PCI Configuration Header\r
347 //\r
348 if (PciRead16 (Address) == MAX_UINT16) {\r
349 if (Function == 0) {\r
350 //\r
351 // If the PCI Configuration Read fails, or a PCI device does not\r
352 // exist, then skip this entire PCI device\r
353 //\r
354 break;\r
355 } else {\r
356 //\r
357 // If PCI function != 0, VendorId == 0xFFFF, we continue to search\r
358 // PCI function.\r
359 //\r
360 continue;\r
361 }\r
362 }\r
363\r
364 //\r
365 // Read the entire PCI Configuration Header\r
366 //\r
367 PciReadBuffer (Address, sizeof (Pci), &Pci);\r
368\r
369 //\r
370 // Increment the number of PCI device found on the primary bus of the\r
371 // PCI root bridge\r
372 //\r
373 NumberOfDevices++;\r
374\r
375 //\r
376 // Look for devices with the VGA Palette Snoop enabled in the COMMAND\r
377 // register of the PCI Config Header\r
378 //\r
379 if ((Pci.Hdr.Command & EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) != 0) {\r
380 Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
381 Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
382 }\r
383\r
384 BarOffsetEnd = 0;\r
385\r
386 //\r
387 // PCI-PCI Bridge\r
388 //\r
389 if (IS_PCI_BRIDGE (&Pci)) {\r
390 //\r
391 // Get the Bus range that the PPB is decoding\r
392 //\r
393 if (Pci.Bridge.SubordinateBus > SubBus) {\r
394 //\r
395 // If the suborinate bus number of the PCI-PCI bridge is greater\r
396 // than the PCI root bridge's current subordinate bus number,\r
397 // then update the PCI root bridge's subordinate bus number\r
398 //\r
399 SubBus = Pci.Bridge.SubordinateBus;\r
400 }\r
401\r
402 //\r
403 // Get the I/O range that the PPB is decoding\r
404 //\r
405 Value = Pci.Bridge.IoBase & 0x0f;\r
406 Base = ((UINT32) Pci.Bridge.IoBase & 0xf0) << 8;\r
407 Limit = (((UINT32) Pci.Bridge.IoLimit & 0xf0) << 8) | 0x0fff;\r
408 if (Value == BIT0) {\r
409 Base |= ((UINT32) Pci.Bridge.IoBaseUpper16 << 16);\r
410 Limit |= ((UINT32) Pci.Bridge.IoLimitUpper16 << 16);\r
411 }\r
412 if ((Base > 0) && (Base < Limit)) {\r
413 if (Io.Base > Base) {\r
414 Io.Base = Base;\r
415 }\r
416 if (Io.Limit < Limit) {\r
417 Io.Limit = Limit;\r
418 }\r
419 }\r
420\r
421 //\r
422 // Get the Memory range that the PPB is decoding\r
423 //\r
424 Base = ((UINT32) Pci.Bridge.MemoryBase & 0xfff0) << 16;\r
425 Limit = (((UINT32) Pci.Bridge.MemoryLimit & 0xfff0) << 16) | 0xfffff;\r
426 if ((Base > 0) && (Base < Limit)) {\r
427 if (Mem.Base > Base) {\r
428 Mem.Base = Base;\r
429 }\r
430 if (Mem.Limit < Limit) {\r
431 Mem.Limit = Limit;\r
432 }\r
433 }\r
434\r
435 //\r
436 // Get the Prefetchable Memory range that the PPB is decoding\r
437 //\r
438 Value = Pci.Bridge.PrefetchableMemoryBase & 0x0f;\r
439 Base = ((UINT32) Pci.Bridge.PrefetchableMemoryBase & 0xfff0) << 16;\r
440 Limit = (((UINT32) Pci.Bridge.PrefetchableMemoryLimit & 0xfff0)\r
441 << 16) | 0xfffff;\r
442 MemAperture = &PMem;\r
443 if (Value == BIT0) {\r
444 Base |= LShiftU64 (Pci.Bridge.PrefetchableBaseUpper32, 32);\r
445 Limit |= LShiftU64 (Pci.Bridge.PrefetchableLimitUpper32, 32);\r
446 MemAperture = &PMemAbove4G;\r
447 }\r
448 if ((Base > 0) && (Base < Limit)) {\r
449 if (MemAperture->Base > Base) {\r
450 MemAperture->Base = Base;\r
451 }\r
452 if (MemAperture->Limit < Limit) {\r
453 MemAperture->Limit = Limit;\r
454 }\r
455 }\r
456\r
457 //\r
458 // Look at the PPB Configuration for legacy decoding attributes\r
459 //\r
460 if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_ISA)\r
461 == EFI_PCI_BRIDGE_CONTROL_ISA) {\r
462 Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;\r
463 Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16;\r
464 Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;\r
465 }\r
466 if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA)\r
467 == EFI_PCI_BRIDGE_CONTROL_VGA) {\r
468 Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
469 Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;\r
470 Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;\r
471 if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA_16)\r
472 != 0) {\r
473 Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
474 Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO_16;\r
475 }\r
476 }\r
477\r
478 BarOffsetEnd = OFFSET_OF (PCI_TYPE01, Bridge.Bar[2]);\r
479 } else {\r
480 //\r
481 // Parse the BARs of the PCI device to get what I/O Ranges, Memory\r
482 // Ranges, and Prefetchable Memory Ranges the device is decoding\r
483 //\r
484 if ((Pci.Hdr.HeaderType & HEADER_LAYOUT_CODE) == HEADER_TYPE_DEVICE) {\r
485 BarOffsetEnd = OFFSET_OF (PCI_TYPE00, Device.Bar[6]);\r
486 }\r
487 }\r
488\r
489 PcatPciRootBridgeParseBars (\r
490 Pci.Hdr.Command,\r
491 PrimaryBus,\r
492 Device,\r
493 Function,\r
494 OFFSET_OF (PCI_TYPE00, Device.Bar),\r
495 BarOffsetEnd,\r
496 &Io,\r
497 &Mem, &MemAbove4G,\r
498 &PMem, &PMemAbove4G\r
499 );\r
500\r
501 //\r
502 // See if the PCI device is an IDE controller\r
503 //\r
504 if (IS_CLASS2 (&Pci, PCI_CLASS_MASS_STORAGE,\r
505 PCI_CLASS_MASS_STORAGE_IDE)) {\r
506 if (Pci.Hdr.ClassCode[0] & 0x80) {\r
507 Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;\r
508 Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;\r
509 }\r
510 if (Pci.Hdr.ClassCode[0] & 0x01) {\r
511 Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;\r
512 }\r
513 if (Pci.Hdr.ClassCode[0] & 0x04) {\r
514 Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;\r
515 }\r
516 }\r
517\r
518 //\r
519 // See if the PCI device is a legacy VGA controller or\r
520 // a standard VGA controller\r
521 //\r
522 if (IS_CLASS2 (&Pci, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA) ||\r
523 IS_CLASS2 (&Pci, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA)\r
524 ) {\r
525 Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
526 Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
527 Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;\r
528 Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;\r
529 Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO_16;\r
530 }\r
531\r
532 //\r
533 // See if the PCI Device is a PCI - ISA or PCI - EISA\r
534 // or ISA_POSITIVIE_DECODE Bridge device\r
535 //\r
536 if (Pci.Hdr.ClassCode[2] == PCI_CLASS_BRIDGE) {\r
537 if (Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA ||\r
538 Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_EISA ||\r
539 Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA_PDECODE) {\r
540 Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;\r
541 Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16;\r
542 Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;\r
543 }\r
544 }\r
545\r
546 //\r
547 // If this device is not a multi function device, then skip the rest\r
548 // of this PCI device\r
549 //\r
550 if (Function == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {\r
551 break;\r
552 }\r
553 }\r
554 }\r
555\r
556 //\r
557 // If at least one PCI device was found on the primary bus of this PCI\r
558 // root bridge, then the PCI root bridge exists.\r
559 //\r
560 if (NumberOfDevices > 0) {\r
561 RootBridges = ReallocatePool (\r
562 (*NumberOfRootBridges) * sizeof (PCI_ROOT_BRIDGE),\r
563 (*NumberOfRootBridges + 1) * sizeof (PCI_ROOT_BRIDGE),\r
564 RootBridges\r
565 );\r
566 ASSERT (RootBridges != NULL);\r
567\r
568 AdjustRootBridgeResource (&Io, &Mem, &MemAbove4G, &PMem, &PMemAbove4G);\r
569\r
570 InitRootBridge (\r
571 Attributes, Attributes, 0,\r
572 (UINT8) PrimaryBus, (UINT8) SubBus,\r
573 &Io, &Mem, &MemAbove4G, &PMem, &PMemAbove4G,\r
574 &RootBridges[*NumberOfRootBridges]\r
575 );\r
576 RootBridges[*NumberOfRootBridges].ResourceAssigned = TRUE;\r
577 //\r
578 // Increment the index for the next PCI Root Bridge\r
579 //\r
580 (*NumberOfRootBridges)++;\r
581 }\r
582 }\r
583\r
584 return RootBridges;\r
585}\r
EFI Development Kit II mirror for PVE