CorebootPayloadPkg: Use SerialDxe in MdeModulePkg
[mirror_edk2.git] / CorebootPayloadPkg / Library / PlatformBdsLib / BdsPlatform.h
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1/** @file\r
2 Head file for BDS Platform specific code\r
3\r
bae5ddc0 4Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
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5This program and the accompanying materials\r
6are licensed and made available under the terms and conditions of the BSD License\r
7which accompanies this distribution. The full text of the license may be found at\r
8http://opensource.org/licenses/bsd-license.php\r
9\r
10THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13**/\r
14\r
15#ifndef _PLATFORM_SPECIFIC_BDS_PLATFORM_H_\r
16#define _PLATFORM_SPECIFIC_BDS_PLATFORM_H_\r
17\r
18#include <PiDxe.h>\r
19#include <IndustryStandard/Pci.h>\r
20#include <Library/DebugLib.h>\r
21#include <Library/BaseMemoryLib.h>\r
22#include <Library/UefiBootServicesTableLib.h>\r
23#include <Library/MemoryAllocationLib.h>\r
24#include <Library/BaseLib.h>\r
25#include <Library/PcdLib.h>\r
26#include <Library/GenericBdsLib.h>\r
27#include <Library/PlatformBdsLib.h>\r
28#include <Library/UefiLib.h>\r
29#include <Library/DevicePathLib.h>\r
30\r
31#include <Protocol/PciIo.h>\r
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32\r
33#include <Guid/GlobalVariable.h>\r
34extern BDS_CONSOLE_CONNECT_ENTRY gPlatformConsole[];\r
35extern EFI_DEVICE_PATH_PROTOCOL *gPlatformConnectSequence[];\r
36extern EFI_DEVICE_PATH_PROTOCOL *gPlatformDriverOption[];\r
37extern EFI_DEVICE_PATH_PROTOCOL *gPlatformRootBridges[];\r
38extern ACPI_HID_DEVICE_PATH gPnp16550ComPortDeviceNode;\r
39extern UART_DEVICE_PATH gUartDeviceNode;\r
40extern VENDOR_DEVICE_PATH gTerminalTypeDeviceNode;\r
41extern VENDOR_DEVICE_PATH gUartDeviceVenderNode;\r
42\r
43//\r
44//\r
45//\r
46#define VarConsoleInpDev L"ConInDev"\r
47#define VarConsoleInp L"ConIn"\r
48#define VarConsoleOutDev L"ConOutDev"\r
49#define VarConsoleOut L"ConOut"\r
50#define VarErrorOutDev L"ErrOutDev"\r
51#define VarErrorOut L"ErrOut"\r
52\r
53#define PCI_DEVICE_PATH_NODE(Func, Dev) \\r
54 { \\r
55 { \\r
56 HARDWARE_DEVICE_PATH, \\r
57 HW_PCI_DP, \\r
58 { \\r
59 (UINT8) (sizeof (PCI_DEVICE_PATH)), \\r
60 (UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8) \\r
61 } \\r
62 }, \\r
63 (Func), \\r
64 (Dev) \\r
65 }\r
66\r
67#define PNPID_DEVICE_PATH_NODE(PnpId) \\r
68 { \\r
69 { \\r
70 ACPI_DEVICE_PATH, \\r
71 ACPI_DP, \\r
72 { \\r
73 (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), \\r
74 (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) \\r
75 }, \\r
76 }, \\r
77 EISA_PNP_ID((PnpId)), \\r
78 0 \\r
79 }\r
80\r
81#define gPciRootBridge \\r
82 PNPID_DEVICE_PATH_NODE(0x0A03)\r
83#define gPnp16550ComPort \\r
84 PNPID_DEVICE_PATH_NODE(0x0501)\r
85\r
86#define gUartVender \\r
87 { \\r
88 { \\r
89 HARDWARE_DEVICE_PATH, \\r
90 HW_VENDOR_DP, \\r
91 { \\r
92 (UINT8) (sizeof (VENDOR_DEVICE_PATH)), \\r
93 (UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8) \\r
94 } \\r
95 }, \\r
bae5ddc0 96 {0xD3987D4B, 0x971A, 0x435F, {0x8C, 0xAF, 0x49, 0x67, 0xEB, 0x62, 0x72, 0x41}} \\r
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97 }\r
98 \r
99#define gUart \\r
100 { \\r
101 { \\r
102 MESSAGING_DEVICE_PATH, \\r
103 MSG_UART_DP, \\r
104 { \\r
105 (UINT8) (sizeof (UART_DEVICE_PATH)), \\r
106 (UINT8) ((sizeof (UART_DEVICE_PATH)) >> 8) \\r
107 } \\r
108 }, \\r
109 0, \\r
110 115200, \\r
111 8, \\r
112 1, \\r
113 1 \\r
114 }\r
115\r
116#define gPcAnsiTerminal \\r
117 { \\r
118 { \\r
119 MESSAGING_DEVICE_PATH, \\r
120 MSG_VENDOR_DP, \\r
121 { \\r
122 (UINT8) (sizeof (VENDOR_DEVICE_PATH)), \\r
123 (UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8) \\r
124 } \\r
125 }, \\r
126 DEVICE_PATH_MESSAGING_PC_ANSI \\r
127 }\r
128\r
129#define gEndEntire \\r
130 { \\r
131 END_DEVICE_PATH_TYPE, \\r
132 END_ENTIRE_DEVICE_PATH_SUBTYPE, \\r
133 { \\r
134 END_DEVICE_PATH_LENGTH, \\r
135 0 \\r
136 } \\r
137 }\r
138#define PCI_CLASS_SCC 0x07\r
139#define PCI_SUBCLASS_SERIAL 0x00\r
140#define PCI_IF_16550 0x02\r
141#define IS_PCI_16550SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)\r
142\r
143#define IS_PCI_ISA_PDECODE(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA_PDECODE, 0)\r
144\r
145//\r
146// Platform Root Bridge\r
147//\r
148typedef struct {\r
149 ACPI_HID_DEVICE_PATH PciRootBridge;\r
150 EFI_DEVICE_PATH_PROTOCOL End;\r
151} PLATFORM_ROOT_BRIDGE_DEVICE_PATH;\r
152EFI_STATUS\r
153PlatformBdsNoConsoleAction (\r
154 VOID\r
155 );\r
156VOID\r
157PlatformBdsEnterFrontPage (\r
158 IN UINT16 TimeoutDefault,\r
159 IN BOOLEAN ConnectAllHappened\r
160 );\r
161#endif // _PLATFORM_SPECIFIC_BDS_PLATFORM_H_\r