FW: [PATCH 3/9] CorebootPayloadPkg/PlatformBdsLib: Fix spelling error

[mirror_edk2.git] / CorebootPayloadPkg / Library / PlatformBdsLib / BdsPlatform.h

/** @file\r
  Head file for BDS Platform specific code\r
\r
Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef _PLATFORM_SPECIFIC_BDS_PLATFORM_H_\r
#define _PLATFORM_SPECIFIC_BDS_PLATFORM_H_\r
\r
#include <PiDxe.h>\r
#include <IndustryStandard/Pci.h>\r
#include <Library/DebugLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/BaseLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/GenericBdsLib.h>\r
#include <Library/PlatformBdsLib.h>\r
#include <Library/UefiLib.h>\r
#include <Library/DevicePathLib.h>\r
\r
#include <Protocol/PciIo.h>\r
\r
#include <Guid/GlobalVariable.h>\r
extern BDS_CONSOLE_CONNECT_ENTRY  gPlatformConsole[];\r
extern EFI_DEVICE_PATH_PROTOCOL   *gPlatformConnectSequence[];\r
extern EFI_DEVICE_PATH_PROTOCOL   *gPlatformDriverOption[];\r
extern EFI_DEVICE_PATH_PROTOCOL   *gPlatformRootBridges[];\r
extern ACPI_HID_DEVICE_PATH       gPnp16550ComPortDeviceNode;\r
extern UART_DEVICE_PATH           gUartDeviceNode;\r
extern VENDOR_DEVICE_PATH         gTerminalTypeDeviceNode;\r
extern VENDOR_DEVICE_PATH         gUartDeviceVendorNode;
\r
//\r
//\r
//\r
#define VarConsoleInpDev        L"ConInDev"\r
#define VarConsoleInp           L"ConIn"\r
#define VarConsoleOutDev        L"ConOutDev"\r
#define VarConsoleOut           L"ConOut"\r
#define VarErrorOutDev          L"ErrOutDev"\r
#define VarErrorOut             L"ErrOut"\r
\r
#define PCI_DEVICE_PATH_NODE(Func, Dev) \\r
  { \\r
    { \\r
      HARDWARE_DEVICE_PATH, \\r
      HW_PCI_DP, \\r
      { \\r
        (UINT8) (sizeof (PCI_DEVICE_PATH)), \\r
        (UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8) \\r
      } \\r
    }, \\r
    (Func), \\r
    (Dev) \\r
  }\r
\r
#define PNPID_DEVICE_PATH_NODE(PnpId) \\r
  { \\r
    { \\r
      ACPI_DEVICE_PATH, \\r
      ACPI_DP, \\r
      { \\r
        (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), \\r
        (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) \\r
      }, \\r
    }, \\r
    EISA_PNP_ID((PnpId)), \\r
    0 \\r
  }\r
\r
#define gPciRootBridge \\r
  PNPID_DEVICE_PATH_NODE(0x0A03)\r
#define gPnp16550ComPort \\r
  PNPID_DEVICE_PATH_NODE(0x0501)\r
\r
#define gUartVendor \
  { \\r
    { \\r
      HARDWARE_DEVICE_PATH, \\r
      HW_VENDOR_DP, \\r
      { \\r
        (UINT8) (sizeof (VENDOR_DEVICE_PATH)), \\r
        (UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8) \\r
      } \\r
    }, \\r
    {0xD3987D4B, 0x971A, 0x435F, {0x8C, 0xAF, 0x49, 0x67, 0xEB, 0x62, 0x72, 0x41}} \\r
  }\r
    \r
#define gUart \\r
  { \\r
    { \\r
      MESSAGING_DEVICE_PATH, \\r
      MSG_UART_DP, \\r
      { \\r
        (UINT8) (sizeof (UART_DEVICE_PATH)), \\r
        (UINT8) ((sizeof (UART_DEVICE_PATH)) >> 8) \\r
      } \\r
    }, \\r
    0, \\r
    115200, \\r
    8, \\r
    1, \\r
    1 \\r
  }\r
\r
#define gPcAnsiTerminal \\r
  { \\r
    { \\r
      MESSAGING_DEVICE_PATH, \\r
      MSG_VENDOR_DP, \\r
      { \\r
        (UINT8) (sizeof (VENDOR_DEVICE_PATH)), \\r
        (UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8) \\r
      } \\r
    }, \\r
    DEVICE_PATH_MESSAGING_PC_ANSI \\r
  }\r
\r
#define gEndEntire \\r
  { \\r
    END_DEVICE_PATH_TYPE, \\r
    END_ENTIRE_DEVICE_PATH_SUBTYPE, \\r
    { \\r
      END_DEVICE_PATH_LENGTH, \\r
      0 \\r
    } \\r
  }\r
#define PCI_CLASS_SCC          0x07\r
#define PCI_SUBCLASS_SERIAL    0x00\r
#define PCI_IF_16550           0x02\r
#define IS_PCI_16550SERIAL(_p)           IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)\r
\r
#define IS_PCI_ISA_PDECODE(_p)        IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA_PDECODE, 0)\r
\r
//\r
// Platform Root Bridge\r
//\r
typedef struct {\r
  ACPI_HID_DEVICE_PATH      PciRootBridge;\r
  EFI_DEVICE_PATH_PROTOCOL  End;\r
} PLATFORM_ROOT_BRIDGE_DEVICE_PATH;\r
EFI_STATUS\r
PlatformBdsNoConsoleAction (\r
  VOID\r
  );\r
VOID\r
PlatformBdsEnterFrontPage (\r
  IN UINT16                 TimeoutDefault,\r
  IN BOOLEAN                ConnectAllHappened\r
  );\r
#endif // _PLATFORM_SPECIFIC_BDS_PLATFORM_H_\r